Pulse-latch based bus design for increased bandwidth
US-2015363352-A1 · Dec 17, 2015 · US
Integrated circuit package with multiple dies and a multiplexed communications interface
US9105316B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105316-B2 |
| Application number | US-201314101444-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 10, 2013 |
| Priority date | Dec 7, 2009 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
Official abstract text for this publication.
A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control signals and the memory transactions onto the interface such that connections of the interface are shared by the control signals and the memory transactions.
First claim
Opening claim text (preview).
What is claimed is: 1. A package, comprising: a first die; a second die; an interface configured to connect the first die and the second die, at least one of the first and second dies comprising a memory, the interface being configured to transport both control signals and memory transactions in packets; and a multiplexer configured to multiplex the control signals and the memory transactions onto the interface such that a plurality of connections of the interface are shared…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- G06F13/16Primary
Physics · mapped topic
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- What does patent US9105316B2 cover?
- A package includes a first die and a second die. An interface connects the first die and the second die. At least one of the first and second dies includes a memory. The interface is configured to transport both control signals and memory transactions. A multiplexing circuit multiplexes the control signals and the memory transactions onto the interface such that connections of the interface are…
- Who is the assignee on this patent?
- St Microelectronics Res & Dev, St Microelectronics Srl
- What technology area does this patent fall under?
- Primary CPC classification G06F13/16. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).