Outer product-based matrix-vector multiplication operation apparatus for accelerating vector operation and method using the same
US-2024362297-A1 · Oct 31, 2024 · US
Variable precision floating point multiply-add circuit
US9104474B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104474-B2 |
| Application number | US-201213730390-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 28, 2012 |
| Priority date | Dec 28, 2012 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
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Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.
First claim
Opening claim text (preview).
What is claimed is: 1. A variable precision floating point circuit comprising: a variable precision mantissa unit to selectively operate in any one of a plurality of precision modes wherein in each precision mode a level of parallelism in the variable precision floating point circuit is inversely proportional to a level of precision, multiple exponent units to selectively operate in one of a plurality of parallelism modes corresponding to a selected precision mode, and certain…
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Physics · mapped topic
Physics · mapped topic
- G06F7/483Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US9104474B2 cover?
- Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inpu…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F7/483. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).