Delay testing capturing second response to first response as stimulus

Patent metadata

Field	Value
Publication number	US-9103886-B2
Application number	US-201414173492-A
Country	US
Kind code	B2
Filing date	Feb 5, 2014
Priority date	Sep 20, 2000
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

First claim

What is claimed is:

1. A process of delay testing logic circuitry, comprising:
A. enabling shifting of parallel connected, equal length subdivisions of a divided scan path;
B. shifting sequentially and separately respective portions of a test pattern of stimulus bits, originally produced for a contiguous scan path, from a single lead through each of the parallel connected, equal length subdivisions of a divided scan path;
C. applying the stimulus bits from each subdivision of…

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D
• Graber Joel J

Classifications

• G01R31/3177

  Physics · mapped topic

• G01R31/318547

  Physics · mapped topic

• G01R31/318541

  Physics · mapped topic

• G01R31/318575

  Physics · mapped topic

• G01R31/318586

  Physics · mapped topic