Semiconductor test system and method
US-9417283-B2 · Aug 16, 2016 · US
De-embedding on-wafer devices
US9103884B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9103884-B2 |
| Application number | US-96351110-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 8, 2010 |
| Priority date | Mar 5, 2008 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.
First claim
Opening claim text (preview).
What is claimed is: 1. A test structure for de-embedding an on-wafer device, the test structure comprising: a first dummy component including a first transmission line; a second dummy component coupled with the first dummy component, wherein the second dummy component includes a second transmission line; and a device-under-test (DUT) electrically coupled with the first dummy component and/or the second dummy component, wherein the first transmission line and the second trans…
Assignees
Inventors
Classifications
Electricity · mapped topic
- G01R31/318511Primary
Physics · mapped topic
Physics · mapped topic
- G01R31/2601Primary
Physics · mapped topic
- G11C29/56Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9103884B2 cover?
- A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate …
- Who is the assignee on this patent?
- Yen Hsiao-Tsung, Lin Yu-Ling, Kuo Chin-Wei, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318511. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).