Fault Detection Circuit for a PWM Driver, Related System and Integrated Circuit
US-2017328953-A1 · Nov 16, 2017 · US
Method and evaluation device for checking plausibility of an incremental counter
US9103883B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9103883-B2 |
| Application number | US-201414172160-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 4, 2014 |
| Priority date | Feb 6, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method and evaluation device for checking plausibility of an incremental counter, wherein counting pulses are detectable via the incremental counter, and wherein a dynamic system generates the counting pulses with a clock rate corresponding to a state of the dynamic system. Here, a minimum value and a maximum value for a possible or permitted change in the clock rate per time unit is predefined based on operating limits of the dynamic system, wherein a current clock rate is calculated in each case from two counting pulses respectively detected last, and wherein at each newly detected counting pulse the counting pulse is checked to determine if the difference between the clock rate calculated in the course of the newly detected counting pulse and a clock rate calculated immediately beforehand is within the limits defined by the minimum value and maximum value, wherein otherwise implausibility is detected.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for checking plausibility of an incremental counter, counting pulses being detected via an incremental counter, a dynamic system generating the counting pulses with a clock rate corresponding to a state of the dynamic system, a minimum acceleration/deceleration value and a maximum acceleration/deceleration value for a possible or permitted change in the clock rate per time unit being predefined on the basis of operating limits of the dynamic system,…
Assignees
Inventors
Classifications
- G01R31/3181Primary
Physics · mapped topic
- G01D5/24461Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9103883B2 cover?
- A method and evaluation device for checking plausibility of an incremental counter, wherein counting pulses are detectable via the incremental counter, and wherein a dynamic system generates the counting pulses with a clock rate corresponding to a state of the dynamic system. Here, a minimum value and a maximum value for a possible or permitted change in the clock rate per time unit is predefin…
- Who is the assignee on this patent?
- Wallner Lorenz, Siemens Ag
- What technology area does this patent fall under?
- Primary CPC classification G01R31/3181. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).