Method for manufacturing silicon wafer and silicon wafer
US-2024304458-A1 · Sep 12, 2024 · US
Process for modifying the properties of a thin layer and substrate applying said process
US9102518B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9102518-B2 |
| Application number | US-47054009-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2009 |
| Priority date | May 7, 2002 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
The invention relates to a process for modifying the properties of a thin layer ( 1 ) formed on the surface of a support ( 2 ) forming a substrate ( 3 ) utilized in the field of microelectronics, nanoelectronics or microtechnology, nanotechnology, characterized in that it consists of: forming at least one thin layer ( 1 ) on a nanostructured support with high specific surface ( 2 ), and treating the nanostructured support with high specific surface ( 2 ) to generate internal strains in the support causing its deformation at least in the plane of the thin layer so as to ensure corresponding deformation of the thin layer to modify its properties.
First claim
Opening claim text (preview).
The invention claimed is: 1. A substrate for microelectronics, nanoelectronics, or for microtechnology, nanotechnology, comprising: a nanostructured support on which is formed at least one thin layer in contact with a surface of the nanostructured support, wherein said surface of the nanostructured support comprises at least one layer of nanocrystallites and/or nanoparticles, and at least one dimension less than or equal to 1,000 nm, wherein the sum of the surfaces of each nanoc…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9102518B2 cover?
- The invention relates to a process for modifying the properties of a thin layer ( 1 ) formed on the surface of a support ( 2 ) forming a substrate ( 3 ) utilized in the field of microelectronics, nanoelectronics or microtechnology, nanotechnology, characterized in that it consists of: forming at least one thin layer ( 1 ) on a nanostructured support with high specific surface ( 2 ), and treatin…
- Who is the assignee on this patent?
- Marty Olivier, Lysenko Volodymyr, Univ Claude Bernard Lyon
- What technology area does this patent fall under?
- Primary CPC classification H10P36/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).