Method of preventing pattern collapse

Patent metadata

Field	Value
Publication number	US-9502287-B2
Application number	US-201514873301-A
Country	US
Kind code	B2
Filing date	Oct 2, 2015
Priority date	Mar 11, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1<y1), a top and bottom width (x2, y2) of a second conducting feature has a dimension of (x2<y2; x2=y2; or x2>y2), and a top and bottom width (x3, y3) of a third conducting feature has a dimension of (x3>y3). The device also includes a gap structure isolating the first and second conducting features. The gap structure can include such things as air or dielectric.

First claim

What is claimed is:

1. A method of forming a device, the method comprising:
receiving a substrate;
forming a first trench in the substrate;
forming a first barrier layer on bottom and side walls of the first trench;
forming a conducting material over the first barrier layer in the first trench;
performing an etching process on the conducting material using a hard mask to form first and second conducting features isolated by a gap structure, wherein the first conducting fea…

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ting Chih-Yuan
• Wu Chung-Wen
• Chen Jeng-Shiou
• Tsai Jang-Shiang
• Shieh Jyu-Horng

Classifications

• H10W20/0633

  Electricity · mapped topic

• H10P50/71

  Electricity · mapped topic

• H10W20/495

  Electricity · mapped topic

• H10W20/425

  Electricity · mapped topic

• H10W20/098

  Electricity · mapped topic