Current sensor for a printed circuit board
US-2024237215-A1 · Jul 11, 2024 · US
Substrate with built-in component
US9101075B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9101075-B2 |
| Application number | US-201314101026-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 9, 2013 |
| Priority date | Sep 12, 2013 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
Official abstract text for this publication.
There is provided a substrate with built-in component, including a metal core layer having a cavity for storing a component; a wiring layer that is laminated on the core layer and has a plurality of vias for an interlayer connection, the vias being formed at regions opposing to the cavity; and an electronic component including a plurality of terminals electrically connected to the plurality of vias, and a component body that is stored in the cavity and has a support surface for supporting the plurality of terminals, the plurality of terminals being disposed eccentrically from a center of the support surface to a first direction, and the component body being disposed eccentrically from a center of the cavity to a second direction opposite to the first direction.
First claim
Opening claim text (preview).
What is claimed is: 1. A substrate with built-in component, comprising: a metal core layer having a cavity for storing a component, the cavity being formed by a single aperture; a wiring layer that is laminated on the core layer and has a plurality of vias for an interlayer connection, the vias being formed at regions opposing to the cavity; and an electronic component including a plurality of terminals electrically connected to the plurality of vias, and a component body that…
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Frequently asked questions
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- What does patent US9101075B2 cover?
- There is provided a substrate with built-in component, including a metal core layer having a cavity for storing a component; a wiring layer that is laminated on the core layer and has a plurality of vias for an interlayer connection, the vias being formed at regions opposing to the cavity; and an electronic component including a plurality of terminals electrically connected to the plurality of …
- Who is the assignee on this patent?
- Taiyo Yuden Kk, Taiyo Yuden Kk
- What technology area does this patent fall under?
- Primary CPC classification H05K1/185. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).