Manufacturing method of non-volatile storage device, and non-volatile storage device

Patent metadata

Field	Value
Publication number	US-9099646-B2
Application number	US-201313778971-A
Country	US
Kind code	B2
Filing date	Feb 27, 2013
Priority date	Aug 10, 2012
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

A manufacturing method includes forming a laminated body on a substrate. A mask layer is formed on the laminated body, and then a portion of the mask layer is removed to form an opening. Then, using the mask layer as a template, a first portion of the laminated body is removed to expose a portion of the substrate beneath the laminated body. The substrate is processed to alter the ratio between the size of mask opening and the removed first portion. A variable resistance layer is then deposited on exposed portions of the mask layer, the laminated body, and the substrate. Then the variable resistance layer is processed to remove at least a portion covering the substrate to permit contact with the underlying substrate. A second electrode layer is deposited to fill the removed portions of the laminated body.

First claim

What is claimed is:

1. A memory cell array, comprising:
at least one memory stack having alternating layers of insulator and electrode materials formed over a peripheral circuit region on a substrate;
a plurality of layered bodies comprising alternating layers of an electrode material and an insulating material extending from an insulating region overlying a surface of the peripheral circuit region and located adjacent to, and offset from, the location of a contact plug to eithe…

Assignees

• Toshiba Kk

Inventors

• Inokuma Hideki
• Yamamoto Kazuhiko

Classifications

• H01L45/146

  Electricity · mapped topic

• H01L45/1608 Primary

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic

• H01L45/1616

  Electricity · mapped topic