Methods to characterize an embedded interface of a CMOS gate stack

Patent metadata

Field	Value
Publication number	US-9099488-B2
Application number	US-201314134291-A
Country	US
Kind code	B2
Filing date	Dec 19, 2013
Priority date	May 24, 2012
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. Surface treatments can be inserted at three possible steps during the formation of the MOSCAP structures. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

First claim

What is claimed is:

1. A method for screening gate stacks, the method comprising
providing a semiconductor substrate;
forming a first oxide layer on the substrate;
defining a plurality of site-isolated regions (SIRs) on the first oxide layer;
patterning the first oxide layer in each SIR to form an active area on a surface of the substrate within each SIR;
applying a first surface treatment to at least one of the SIRs in a combinatorial manner;
forming a second oxide laye…

Assignees

• Intermolecular Inc

Inventors

• Niyogi Sandip
• Pramanik Dipankar

Classifications

• H10P74/207

  Electricity · mapped topic

• H10P74/23

  Electricity · mapped topic

• H10D1/047 Primary

  Electricity · mapped topic

• H01L29/66181 Primary

  Electricity · mapped topic

• H01L22/14

  Electricity · mapped topic