Semiconductor die, semiconductor package and substrate dicing method
US-2024421000-A1 · Dec 19, 2024 · US
Methods and apparatus of guard rings for wafer-level-packaging
US9099485B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099485-B2 |
| Application number | US-201213419126-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2012 |
| Priority date | Mar 13, 2012 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
Official abstract text for this publication.
Methods and apparatuses are disclosed for forming a post-passivation interconnect (PPI) guard ring over a circuit in a wafer forming a wafer level package (WLP). A circuit device comprises a guard ring and an active area. A passivation layer is formed on top of the circuit device over the guard ring and the active area, wherein the passivation layer contains a passivation contact connected to the guard ring. A first polymer layer is formed over the passivation layer. A PPI opening is formed within the first polymer layer or within the passivation layer over the passivation contact. A PPI guard ring is formed filling the PPI opening in touch with the passivation contact and extending on top of the first polymer layer or the passivation layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a circuit device comprising a guard ring and an active area; a passivation layer on the circuit device over the guard ring and the active area, wherein the passivation layer comprises a passivation contact connected to the guard ring; a first polymer layer over the passivation layer, wherein the first polymer layer has a post-passivation interconnect (PPI) opening over the guard ring; a PPI guard ring filling the PPI…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9099485B2 cover?
- Methods and apparatuses are disclosed for forming a post-passivation interconnect (PPI) guard ring over a circuit in a wafer forming a wafer level package (WLP). A circuit device comprises a guard ring and an active area. A passivation layer is formed on top of the circuit device over the guard ring and the active area, wherein the passivation layer contains a passivation contact connected to t…
- Who is the assignee on this patent?
- Yu Tsung-Yuan, Chen Hsien-Wei, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W42/121. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).