E-fuse structure design in electrical programmable redundancy for embedded memory circuit

Patent metadata

Field	Value
Publication number	US-9099467-B2
Application number	US-201314107917-A
Country	US
Kind code	B2
Filing date	Dec 16, 2013
Priority date	Jun 29, 2004
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

First claim

What is claimed is:

1. A method comprising:
applying a voltage differential between an anode of a fuse and a cathode of the fuse, wherein a first number of conductive vias extend from the anode and are electrically coupled between the anode and the cathode, wherein a second number of conductive vias extend from the cathode and are electrically coupled between the anode and the cathode, the first number being different than the second number;
wherein the voltage differential form…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Thei Kong-Beng
• Cheng Chung Long
• Liu Chung-Shi
• Chuang Harry-Hak-Lay
• Wu Shien-Yang
• Chen Shi-Bai

Classifications

• H10W20/425

  Electricity · mapped topic

• H10W20/47

  Electricity · mapped topic

• H10W20/493 Primary

  Electricity · mapped topic

• H01L23/5256 Primary

  Electricity · mapped topic

• H01L2924/0002

  Electricity · mapped topic