Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Semiconductor device manufacturing methods
US9099400B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099400-B2 |
| Application number | US-201314042253-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 30, 2013 |
| Priority date | Sep 30, 2013 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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Abstract
Official abstract text for this publication.
Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming a first pattern in a hard mask using a first lithography process; forming a second pattern in the hard mask using a second lithography process; forming a protective layer over the hard mask; and forming a first masking layer over the protective layer; patterning the first masking layer into a mandrel; conformally forming a second masking layer on the mandrel; removin…
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Classifications
- H10P76/4085Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9099400B2 cover?
- Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protectiv…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).