Photodiodes and fabrication thereof

Patent metadata

Field	Value
Publication number	US-9087755-B2
Application number	US-59717708-A
Country	US
Kind code	B2
Filing date	Mar 28, 2008
Priority date	Apr 24, 2007
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A photodiode includes an anode ( 1202, 1302, 1402 ) and a cathode ( 1306, 1406 ) formed on a semiconductor substrate ( 402 ). A vertical electrode ( 702, 1314, 1414 ) is in operative electrical communication with a buried component ( 502, 1312, 1412 ) of the photodiode. In one implementation, the photodiode is an avalanche photodiode of a silicon photomultiplier. The substrate may also include integrated CMOS readout circuitry ( 1102 ).

First claim

Having thus described the preferred embodiments, the invention is now claimed to be:

1. A Geiger-mode avalanche photodiode comprising:
a diode, including:
a cathode of the diode that receives incident radiation;
an anode of the same diode located with respect to the cathode along a direction of the incident radiation;

a first epitaxial layer located between the anode and the cathode along the direction of the incident radiation;
an electrically conductive guard ring located in the first epitaxial layer between the cathode and the anode along the direction of the incident radiation;
a vertical electrode located in the first epitaxial layer between the cathode and the anode along the direction of the incident radiation, wherein the vertical electrode is in operative electrical communication with the guard ring and provides an electrical connection to the guard ring; and
an isolation trench that surrounds the vertical electrode and the electrically conductive guard ring.

2. The photodiode of claim 1 wherein the electrically conductive guard ring includes a buried semiconductor layer, and the Geiger-mode avalanche photodiode includes a semiconductor substrate and readout circuitry, wherein the photodiode and the readout circuitry are formed on the substrate, the vertical electrode and the buried semiconductor layer form an isolation well, and the readout circuitry is located outside the isolation well.

3. The photodiode of claim 2 wherein the buried layer is formed by shallow implantation or diffusion of the first epitaxial layer and the photodiode includes a second epitaxial layer grown over the buried layer.

4. The photodiode of claim 1 including a substrate and CMOS circuitry, wherein the photodiode and the circuitry are formed on the substrate, and the photodiode includes a field enhancement region formed prior to the formation of the CMOS circuitry.

5. The photodiode of claim 4 wherein the field enhancement region is formed by implantation.

6. The photodiode of claim 1 wherein the isolation trench further surrounds the first epitaxial layer of the photodiode, wherein the vertical electrode is located at a side of the isolation trench that faces the active region.

7. The photodiode of claim 6 wherein the vertical electrode is formed by implantation, diffusion, or epitaxy.

8. The photodiode of claim 1 wherein the vertical electrode is in operative electrical communication with the guard ring.

9. The photodiode of claim 8 wherein the photodiode includes a field enhancement region, and wherein the electrically conductive guard ring is located below the field enhancement region.

10. A method of producing a semiconductor device that includes a Geiger-mode avalanche photodiode, the method comprising:
forming a cathode of a photodiode, the cathode comprising a photosensitive surface which receives incident radiation;
forming an anode of the photodiode, the anode located with respect to the cathode in a direction of the incident radiation on the photosensitive surface and parallel with an offset from the cathode;
forming a deep isolation trench in a semiconductor material;
forming an electrically conductive guard ring of the photodiode in the semiconductor material, wherein the electrically conductive guard ring is between the cathode and the anode in the direction of the incident radiation and is surrounded by the deep isolation trench; and
forming an electrode along a sidewall of the isolation trench, wherein the electrode is located between the cathode and the anode in the direction of the incident radiation and provides an electrical connection to the electrically conductive guard ring.

11. The method of claim 10 wherein the semiconductor device includes CMOS circuitry and the method includes
forming a field enhancement region in the semiconductor material;
processing the CMOS circuitry; and
annealing the semiconductor material to repair a defect resulting from the formation of the field enhancement region, wherein the step of annealing is performed prior to the step of processing.

12. The method of claim 10 wherein the semiconductor device includes CMOS circuitry and the method includes depositing a metal in the isolation trench during a back end of line processing of the CMOS circuitry.

13. The method of claim 10 wherein the semiconductor devices includes CMOS circuitry and the method includes forming a photodiode optical window during a back end of line processing of the CMOS circuitry.

14. The method of claim 10 wherein the electrically conductive guard ring is a buried layer and the electrode and the buried layer form an isolation well that surrounds a region of the photodiode.

15. The method of claim 10 including
forming the buried layer by shallow implantation or diffusion;
growing an epitaxial layer over the buried layer.

16. The method of claim 10 wherein the component is a buried guard ring.

17. The method of claim 10 wherein forming the deep trench includes etching the trench to a first depth prior to the formation of the electrode and etching the trench to a second depth following the formation of the electrode.

18. The method of claim 10 wherein the semiconductor material includes a highly doped substrate and wherein a field plate is operatively electrically connected to the substrate.

Assignees

• Frach Thomas
• Koninkl Philips Nv

Inventors

• Frach Thomas

Classifications

• Y02E10/547

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• H10F39/807

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• H10F77/206

  for devices having potential barriers · CPC title

• H10F77/148

  Shapes of potential barriers · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title