Nonvolatile semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9087715-B2
Application number	US-201213547645-A
Country	US
Kind code	B2
Filing date	Jul 12, 2012
Priority date	Jul 15, 2011
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a structure comprising first and second memory cells stacked in a first direction perpendicular to the surface of the semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate; and
a beam,
wherein the beam is connected to an end of the structure in the second direction and extends in a third direction perpendicular to the first and second directions,
the structure and the beam each comprises first and second semiconductor layers stacked in the first direction,
the first and second memory cells correspond to the first and second semiconductor layers in the structure,
the beam comprises a contact portion in which the first and second semiconductor layers in the beam are in contact with plugs respectively at one end of the beam in the third direction, and a low resistance portion having a resistance value lower than that of the first and second semiconductor layers,
the low resistance portion extends from the contact portion to the end of the structure, and
the contact portion has a stepped shape that exposes the first and second semiconductor layers, and comprises the low resistance portion, in the first and second semiconductor layers exposed by the stepped shape.

2. The device of claim 1 ,
wherein the low resistance portion is an impurity region in which an impurity is implanted in the first and second semiconductor layers.

3. The device of claim 2 ,
wherein the impurity region is formed on the side surfaces of the first and second semiconductor layers.

4. The device of claim 1 ,
wherein the low resistance portion comprises one of substances selected from the group consisting of TaN, TaC, and TiN, or one of substances selected from the group consisting of Ni, V, Cr, Mn, Y, Mo, Ru, Rh, Hf, Ta, W, Ir, Co, Ti, Er, Pt, Pd, Zr, Gd, Dy, Ho, and Er or a silicide thereof.

5. The device of claim 1 , further comprising
a layer select transistor which selects one of the first and second semiconductor layers; and a common contact plug connected to the first and second semiconductor layers in the contact portion.

6. The device of claim 1 , further comprising
a common electrode which passes through the fin type stacked layer structure and which is connected to the first and second semiconductor layers.

7. The device of claim 1 , further comprising
an assist gate transistor which is disposed between the first memory cell and the beam and between the second memory cell and the beam, and which serves as an FET using the first and second semiconductor layers as channels.

8. The device of claim 1 ,
wherein each of the first and second memory cells is an FET which comprises a recording layer and a gate electrode and which uses the first and second semiconductor layers as channels and which changes in threshold in accordance with the state of the recording layer.

9. The device of claim 1 , further comprising a third semiconductor layer which is disposed between the first and second semiconductor layers and which extends in the third direction;
wherein the first memory cell is a resistance change element disposed between the first and third semiconductor layers, and the second memory cell is a resistance change element disposed between the second and third semiconductor layers, and
the first, second and third semiconductor layers function as electrically conductive layers, respectively.

10. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
a structure comprising first and second memory cells stacked in a first direction perpendicular to the surface of the semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate; and
a beam,
wherein the beam is connected to an end of the structure in the second direction and extends in a third direction perpendicular to the first and second directions,
the structure and the beam each comprises first and second semiconductor layers stacked in the first direction,
the first and second memory cells correspond to the first and second semiconductor layers in the structure,
the beam comprises a contact portion in which the first and second semiconductor layers in the beam are in contact with plugs respectively at one end of the beam in the third direction, and a low resistance portion having a resistance value lower than that of the first and second semiconductor layers,
the low resistance portion extends from the contact portion to the end of the structure,
the width of the beam in the second direction is greater than the width of the structure in the third direction, and the beam comprises a slit passing through the first and second semiconductor layers, and
the low resistance portion is provided in the surface regions of the first and second semiconductor layers exposed inside the slit.

Assignees

• Kusai Haruka
• Sakuma Kiwamu
• Fujii Shosuke
• Saitoh Masumi
• Kiyotoshi Masahiro
• Toshiba Kk

Inventors

• Kusai Haruka
• Sakuma Kiwamu
• Fujii Shosuke
• Saitoh Masumi
• Kiyotoshi Masahiro

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10P14/29

  characterised by the substrates · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• G11C16/10

  Programming or data input circuits · CPC title