Temperature sensing circuit

Patent metadata

Field	Value
Publication number	US-9086330-B2
Application number	US-201313915236-A
Country	US
Kind code	B2
Filing date	Jun 11, 2013
Priority date	Apr 22, 2009
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

A circuit includes a comparator, a first circuit, and a second circuit. The comparator has a first input node and a second input node. The first circuit is configured to output a temperature-dependent voltage at the first input node of the comparator. The first circuit includes a current mirror configured to generate a first reference voltage. The second circuit is configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

First claim

What is claimed is:

1. A circuit comprising:
a comparator having a first input node and a second input node;
a first circuit configured to output a temperature-dependent voltage at the first input node of the comparator, the first circuit comprising a current mirror configured to generate a first reference voltage; and
a second circuit configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

2. The circuit of claim 1 , wherein the first circuit is configured to generate a complementary-to-absolute-temperature (CTAT) voltage at the first input node of the comparator.

3. The circuit of claim 1 , wherein the current mirror of the first circuit comprises:
an amplifier having a first input node, a second input node, and an output node;
a first transistor having a source coupled to a power node, a drain coupled to the first input node of the amplifier, and a gate coupled to the output node of the amplifier; and
a second transistor having a source coupled to the power node, a drain coupled to the second input node of the amplifier, and a gate coupled to the output node of the amplifier.

4. The circuit of claim 1 , wherein the first circuit further comprises:
a first transistor having a collector coupled to a reference node, a base coupled to the reference node, and an emitter coupled to a first node of the current mirror;
a second transistor having a collector coupled to the reference node, a base coupled to the reference node, and an emitter, a size of the second transistor is greater than that of the first transistor by a predetermined ratio; and
a first resistive device coupled between the second node of the current mirror and the emitter of the second transistor.

5. The circuit of claim 4 , wherein the first circuit further comprises:
a second resistive device coupled between the first node of the current mirror and the reference node; and
a third resistive device coupled between the second node of the current mirror and the reference node.

6. The circuit of claim 1 , wherein the second circuit comprises:
one or more transistors connected in parallel and coupled between the second input node of the comparator and a power node, the one or more transistors having corresponding one or more gates configured to receive the first reference voltage from the current mirror; and
one or more resistive devices connected in parallel and coupled between the second input node of the comparator and a reference node.

7. The circuit of claim 6 , wherein the one or more transistors are configured to be turned on responsive to the digital code.

8. The circuit of claim 6 , wherein the one or more resistive devices are configured to be electrically decoupled from the second input node of the comparator responsive to the digital code.

9. A circuit comprising:
a comparator having a first input node and a second input node;
a first circuit configured to output a temperature-dependent voltage at the first input node of the comparator, the first circuit comprising:
a current mirror configured to generate a first reference voltage;
a first transistor having a source coupled to a power node, a gate configured to receive the first reference voltage, and a drain;
a second transistor having a collector coupled to a reference node, a base coupled to the reference node, and an emitter coupled to the drain of the first transistor;
a first resistive device coupled between a first node of the current mirror and the drain of the first transistor; and
a second resistive device coupled between a second node of the current mirror and the drain of the first transistor; and

a second circuit configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

10. The circuit of claim 9 , wherein the first circuit is configured to generate a complementary-to-absolute-temperature (CTAT) voltage at the first input node of the comparator.

11. The circuit of claim 9 , wherein the current mirror of the first circuit comprises:
an amplifier having a first input node, a second input node, and an output node;
a third transistor having a source coupled to a power node, a drain coupled to the first input node of the amplifier, and a gate coupled to the output node of the amplifier; and
a fourth transistor having a source coupled to the power node, a drain coupled to the second input node of the amplifier, and a gate coupled to the output node of the amplifier.

12. The circuit of claim 9 , wherein the first circuit further comprises:
a third transistor having a collector coupled to the reference node, a base coupled to the reference node, and an emitter coupled to the first node of the current mirror;
a fourth transistor having a collector coupled to the reference node, the base coupled to the reference node, and an emitter, a size of the fourth transistor is greater than that of the third transistor by a predetermined ratio; and
a third resistive device coupled between the second node of the current mirror and the emitter of the fourth transistor.

13. The circuit of claim 12 , wherein the first circuit further comprises:
a fourth resistive device coupled between the first node of the current mirror and the reference node; and
a fifth resistive device coupled between the second node of the current mirror and the reference node.

14. The circuit of claim 9 , wherein the second circuit comprises:
a set of parallel-connected transistors coupled between the second input node of the comparator and the power node, the set of parallel-connected transistors having corresponding one or more gates configured to receive the first reference voltage from the current mirror; and
a set of parallel-connected resistive devices coupled between the second input node of the comparator and the reference node.

15. The circuit of claim 14 , wherein the set of parallel-connected transistors are configured to be turned on responsive to the digital code.

16. The circuit of claim 14 , wherein the set of parallel-connected resistive devices are configured to be electrically decoupled from the second input node of the comparator responsive to the digital code.

17. A circuit comprising:
a comparator having a first input node and a second input node;
a first circuit configured to output a temperature-dependent voltage at the first input node of the comparator, the first circuit comprising:
a current mirror configured to generate a first reference voltage;
a first transistor having a source coupled to a power node, a gate configured to receive the first reference voltage, and a drain; and
a first resistive device coupled between the drain of the first transistor and

a reference node; and
a second circuit configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

18. The circuit of claim 17 , wherein the first circuit is configured to generate a proportional-to-absolute-temperature (PTAT) voltage at the first input node of the comparator.

19. The circuit of claim 17 , wherein the current mirror of the first circuit comprises:
an amplifier having a first input node, a second input node, and an output node;
a second transistor having a source coupled to the power node, a drain coupled to the first input node of the amplifier, and a gate coupled to the output node of the amplifier; and
a third tran

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chern Chan-Hong
• Swei Steven

Classifications

• G01K7/01 Primary

  using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence) · CPC title

• G01K2219/00

  Thermometers with dedicated analog to digital converters · CPC title

• G01K7/14 Primary

  Arrangements for modifying the output characteristic, e.g. linearising · CPC title