Ramp-stack chip package with variable chip spacing

Patent metadata

Field	Value
Publication number	US-9082632-B2
Application number	US-201213468891-A
Country	US
Kind code	B2
Filing date	May 10, 2012
Priority date	May 10, 2012
Publication date	Jul 14, 2015
Grant date	Jul 14, 2015

Abstract

A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.

First claim

What is claimed is:

1. A chip package, comprising:
semiconductor dies arranged in a stack in a vertical direction, which is substantially perpendicular to a plane of a first semiconductor die in the stack, wherein each semiconductor die, after the first semiconductor die, is offset in a horizontal direction in the plane by an offset value from an immediately preceding semiconductor die in the stack, thereby defining a stepped terrace at one side of the stack, and wherein surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies;
connectors electrically and mechanically coupled to the first pads; and
a ramp component positioned on the one side of the stack, wherein the ramp component is approximately parallel to a direction along the stepped terrace, which is between the horizontal direction and the vertical direction;
wherein the ramp component has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies; and
wherein the connectors are electrically and mechanically coupled to the second pads including at least two rows of connectors, wherein a first row of the connectors are coupled to a first row of the first pads and a first row of the second pads, wherein a second row of the connectors are coupled to a second row of the first pads and a second row of the second pads, and wherein the two rows of connectors have at least one of the following configurations: the two rows of connectors have different sizes, the two rows of connectors have different shapes, and at least one of the two rows of connectors have sub-components including pits or pillars, thereby enabling coupling of the first and second pads with variable spacing.

2. The chip package of claim 1 , wherein the connectors include solder balls; and
wherein the connectors are rigidly mechanically coupled to the first pads and the second pads.

3. The chip package of claim 2 , wherein the solder balls have two different sizes; and
wherein a first size of the solder balls is associated with a first row in the two rows of first pads and a second size of the solder balls is associated with a second row in the two rows of first pads.

4. The chip package of claim 2 , wherein the first pads have two different sizes; and
wherein a first size of the first pads is associated with a first row in the two rows of first pads and a second size of the first pads is associated with a second row in the two rows of first pads.

5. The chip package of claim 2 , wherein the second pads have two different sizes; and
wherein a second size of the second pads is associated with a first row in at least the two rows of second pads and a second size of the second pads is associated with a second row in at least the two rows of second pads.

6. The chip package of claim 2 , wherein at least some of the first pads and the second pads have an elliptical shape.

7. The chip package of claim 2 , wherein at least some of the solder balls are compressed more than a remainder of the solder balls.

8. The chip package of claim 1 , wherein the connectors include flexible connectors; and
wherein the connectors are remateably mechanically coupled to the first pads and the second pads.

9. The chip package of claim 8 , wherein the flexible connectors have two different heights; and
wherein a first height of the flexible connectors is associated with a first row in the two rows of first pads and a second height of the flexible connectors is associated with a second row in the two rows of first pads.

10. The chip package of claim 1 , wherein the ramp component includes pillars disposed on the surface and arranged in rows; and
wherein at least one of two rows of second pads for each of the semiconductor dies is disposed on one of the rows of pillars.

11. The chip package of claim 1 , wherein the ramp component includes negative features disposed on the surface and arranged in rows; and
wherein at least one of two rows of second pads for each of the semiconductor dies is disposed in one of the rows of negative features.

12. The chip package of claim 1 , wherein the ramp component is a passive component.

13. The chip package of claim 12 , wherein the passive component includes a plastic substrate with metal traces for electrically coupling to the semiconductor dies.

14. The chip package of claim 1 , wherein the ramp component is another semiconductor die.

15. The chip package of claim 1 , wherein the connector includes an anisotropic conductive film.

16. The chip package of claim 1 , wherein the ramp component facilitates communication of electrical signals and power signals to the semiconductor dies without through-chip vias in the semiconductor dies.

17. The chip package of claim 1 , further comprising an intermediate chip between at least two of the semiconductor dies in the stack, wherein the intermediate chip is configured to transport heat generated by operation of at least the two of the semiconductor dies along the horizontal direction.

18. The chip package of claim 1 , wherein the surfaces of the semiconductor dies include negative features; and
wherein positive features in the negative features maintain relative alignment of the semiconductor dies in the stack.

19. A computer system, comprising:
a processor;
a memory storing a program module that is configured to be executed by the processor; and
a chip package, wherein the chip package includes:
semiconductor dies arranged in a stack in a vertical direction which is substantially perpendicular to a plane of a first semiconductor die in the stack, wherein each semiconductor die, after the first semiconductor die, is offset in a horizontal direction in the plane by an offset value from an immediately preceding semiconductor die in the stack, thereby defining a stepped terrace at one side of the stack, and wherein surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies;
connectors electrically and mechanically coupled to the first pads; and
a ramp component positioned on the one side of the stack, wherein the ramp component is approximately parallel to a direction along the stepped terrace, which is between the horizontal direction and the vertical direction;
wherein the ramp component has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies; and
wherein the connectors are electrically and mechanically coupled to the second pads including at least two rows of connectors, wherein a first row of the connectors are coupled to a first row of the first pads and a first row of the second pads, wherein a second row of the connectors are coupled to a second row of the first pads and a second row of the second pads, and wherein the two rows of connectors have at least one of the following configurations: the two rows of connectors have different sizes, the two rows of connectors have different shapes, and at least one of the two rows of connectors have sub-components including pits or pillars, thereby enabling coupling of the first and second pads with variable spacing.

Assignees

• Dayringer Michael H S
• Nettleton Nyles I
• Hopkins Ii Robert David
• Oracle Int Corp

Inventors

• Dayringer Michael H S
• Nettleton Nyles I
• Hopkins Ii Robert David

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title