Clock control circuitry and methods of utilizing the clock control circuitry

Patent metadata

Field	Value
Publication number	US-9075112-B1
Application number	US-201314108063-A
Country	US
Kind code	B1
Filing date	Dec 16, 2013
Priority date	Dec 27, 2011
Publication date	Jul 7, 2015
Grant date	Jul 7, 2015

Abstract

A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.

First claim

What is claimed is:

1. A method for operating design-for-test circuitry that includes a multiplexer and a counter circuit, wherein the multiplexer includes first and second data inputs and a control input, the method comprising:
receiving a clock polarity control signal at the first data input of the multiplexer;
receiving a selected clock signal at the second data input of the multiplexer;
receiving a counter output signal from the counter circuit at the control input of the…

Assignees

• Altera Corp

Inventors

• Kantipudi Kalyana Ravindra
• Shah Dhwani
• Ghosh Dastidar Jayabrata

Classifications

• G01R31/318572

  Physics · mapped topic

• G01R31/318536

  Physics · mapped topic

• G01R31/318555

  Physics · mapped topic

• G01R31/3177 Primary

  Physics · mapped topic

• G06F1/04

  Physics · mapped topic