Detecting chip alterations with light emission

Patent metadata

Field	Value
Publication number	US-9075106-B2
Application number	US-51216809-A
Country	US
Kind code	B2
Filing date	Jul 30, 2009
Priority date	Jul 30, 2009
Publication date	Jul 7, 2015
Grant date	Jul 7, 2015

Abstract

An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

First claim

What is claimed is:

1. A method comprising:
obtaining a light emission map of a circuit to be tested for alterations;
obtaining a light emission map of a reference circuit; and
comparing an image of said light emission map of said circuit to be tested with an image of said light emission map of said reference circuit, to determine presence of said alterations;
wherein said comparing step comprises at least one of performing image processing to subtract the image of said light emission map of said circuit to be tested from the image of said light emission map of said reference circuit, performing image processing to differentiate the image of said light emission map of said circuit to be tested from the image of said light emission map of said reference circuit, and performing image processing to apply a two-dimensional correlation function to correlate the image of said light emission map of said circuit to be tested and the image of said light emission map of said reference circuit;
wherein said light emission map of said reference circuit is obtained by simulation;
wherein said simulation comprises:
calculating a leakage current for each of a plurality of devices of said reference circuit, based on a layout database and a state vector;
dividing said reference circuit into a plurality of sub-Nyquist tiles;
summing said leakage current for each of said devices in each given one of said sub-Nyquist tiles to obtain a resultant grid; and
oversampling said resultant grid, wherein said oversampling comprises convolving an oversampling window with said sub-Nyquist tiles to provide smoothing; and
wherein said step of obtaining said light emission map of said circuit to be tested, said step of obtaining said light emission map of said reference circuit, and said step of comparing are performed by one or more hardware devices including a memory and at least one processor, coupled to said memory.

2. The method of claim 1 , further comprising normalizing at least one of the image of said light emission map of said circuit to be tested and the image of said light emission map of said reference circuit, prior to said comparing step.

3. The method of claim 2 , wherein said light emission map of said circuit to be tested is obtained by an emission tool.

4. The method of claim 3 , further comprising applying liquid cooling to said circuit to be tested while obtaining said light emission map.

5. The method of claim 3 , further comprising initializing said circuit to be tested prior to said obtaining of said light emission map of said circuit to be tested.

6. The method of claim 1 , wherein said simulation further comprises:
applying a functional form to obtain said light emission map from said leakage currents in said resultant grid.

7. The method of claim 6 , wherein said functional form is based on data gathered using a calibration circuit.

8. The method of claim 2 , wherein said light emission map of said circuit to be tested is obtained using a microscope with an objective lens.

9. The method of claim 8 , further comprising introducing a solid immersion lens between said objective lens of said microscope and said circuit to be tested.

10. The method of claim 2 , wherein said alterations comprise tampering with unused logic.

11. The method of claim 10 , wherein said unused logic comprises unused gate arrays.

12. An apparatus comprising:
means for obtaining a light emission map of a circuit to be tested for alterations;
means for obtaining a light emission map of a reference circuit; and
means for comparing an image of said light emission map of said circuit to be tested with an image of said light emission map of said reference circuit, to determine presence of said alterations;
wherein said means for comparing comprises at least one of means for performing image processing to subtract the image of said light emission map of said circuit to be tested from the image of said light emission map of said reference circuit, means for performing image processing to differentiate the image of said light emission map of said circuit to be tested from the image of said light emission map of said reference circuit, and means for performing image processing to apply a two-dimensional correlation function to correlate the image of said light emission map of said circuit to be tested and the image of said light emission map of said reference circuit;
wherein said means for obtaining said light emission map of said reference circuit comprises:
means for calculating a leakage current for each of a plurality of devices of said reference circuit, based on a layout database and a state vector;
means for dividing said reference circuit into a plurality of sub-Nyquist tiles;
means for summing said leakage current for each of said devices in each given one of said sub-Nyquist tiles to obtain a resultant grid; and
means for oversampling said resultant grid, wherein said oversampling comprises convolving an oversampling window with said sub-Nyquist tiles to provide smoothing.

13. The apparatus of claim 12 , further comprising means for normalizing at least one of the image of said light emission map of said circuit to be tested and the image of said light emission map of said reference circuit, prior to said comparing step.

14. An apparatus comprising:
a memory;
at least one processor, coupled to said memory, said processor being operative to:
obtain a light emission map of a circuit to be tested for alterations;
obtain a light emission map of a reference circuit;
compare an image of said light emission map of said circuit to be tested with an image of said light emission map of said reference circuit, to determine presence of said alterations; and
at least one of perform image processing to subtract the image of said light emission map of said circuit to be tested from the image of said light emission map of said reference circuit, perform image processing to differentiate the image of said light emission map of said circuit to be tested from the image of said light emission map of said reference circuit, and perform image processing to apply a two-dimensional correlation function to correlate the image of said light emission map of said circuit to be tested and the image of said light emission map of said reference circuit; and
an emission prediction module embodied in a computer readable storage medium, said at least one processor being operative to execute said emission prediction module to obtain said light emission map of said reference circuit;
wherein said processor is operative to execute said emission prediction module by:
calculating a leakage current for each of a plurality of devices of said reference circuit, based on a layout database and a state vector;
dividing said reference circuit into a plurality of sub-Nyquist tiles;
summing said leakage current for each of said devices in each given one of said sub-Nyquist tiles to obtain a resultant grid; and
oversampling said resultant grid, wherein said oversampling comprises convolving an oversampling window with said sub-Nyquist tiles to provide smoothing.

15. The apparatus of claim 14 , wherein said at least one processor is further operative to normalize at least one of the image of said light emission map of said circuit to be tested and the image of said light emission map of said reference circuit, prior to said comparing step.

16. The apparatus of claim 15 , wherein said processor is further operative to execute said emission prediction module by:
applying a functional form to obtain said light emission map from said leakage cu

Assignees

• Bernstein Kerry
• Culp James
• Heidel David F
• Pfeiffer Dirk
• Polson Anthony D
• Song Peilin
• Stellari Franco
• Wisnieff Robert L
• IBM

Inventors

• Bernstein Kerry
• Culp James
• Heidel David F
• Pfeiffer Dirk
• Polson Anthony D
• Song Peilin
• Stellari Franco
• Wisnieff Robert L

Classifications

• G01R31/311 Primary

  of integrated circuits {(G01R31/31728 takes precedence)} · CPC title