Semiconductor process

Patent metadata

Field	Value
Publication number	US-9070710-B2
Application number	US-201313912218-A
Country	US
Kind code	B2
Filing date	Jun 7, 2013
Priority date	Jun 7, 2013
Publication date	Jun 30, 2015
Grant date	Jun 30, 2015

Abstract

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.

First claim

What is claimed is:

1. A semiconductor process, comprising:
providing a substrate;
forming at least a fin-shaped structure in the substrate;
forming a gate structure partially overlapping the fin-shaped structure;
blanketly forming a dielectric layer on the substrate;
removing a part of the dielectric layer to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure;
simultaneously removing the second spacer and a part of the f…

Assignees

• United Microelectronics Corp

Inventors

• Fu Ssu-I
• Chen Cheng-Guo
• Hung Yu-Hsiang
• Chang Chung-Fu
• Lin Chien-Ting

Classifications

• H10D30/024

  Electricity · mapped topic

• H10D64/021

  Electricity · mapped topic

• H10D30/797

  Electricity · mapped topic

• H10D64/017 Primary

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic