High-speed divide-by-1.5 circuit with 50 percent duty cycle

Patent metadata

Field	Value
Publication number	US-9065449-B2
Application number	US-201314064247-A
Country	US
Kind code	B2
Filing date	Oct 28, 2013
Priority date	Oct 28, 2013
Publication date	Jun 23, 2015
Grant date	Jun 23, 2015

Abstract

A divide-by-1.5 circuit includes a divide-by-3 circuit that and a frequency doubler circuit. The divide-by-3 circuit has few logic elements and provides glitch-free operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phase-locked loop circuitry.

First claim

What is claimed is:

1. A divide-by-1.5 circuit, comprising:
a divide-by-3 circuit having an input coupleable to a source of an input signal; and
a frequency doubler circuit comprising phase-locked loop (PLL) circuitry, the frequency doubler circuit having an input coupled to an output of the divide-by-3 circuit and having an output defining an output of the divide-by-1.5 circuit, the PLL circuitry having a comparison circuit, a loop filter, a voltage-controlled oscillator (VCO), and a loop divider circuit, the comparison circuit having a first input defining the input of the frequency doubler circuit, the loop divider circuit having an input coupled to an output of the VCO and an output coupled to a second input of the comparison circuit, an output of the VCO defining an output of the frequency doubler circuit, the loop filter connected to an output of the comparison circuit and an input of the VCO, the frequency doubler circuit coupled to a pre-divide-by-2 circuit having an output coupled to the first input of the comparison circuit, wherein the loop divider circuit comprises a loop divide-by-4 circuit including two loop divide-by-2 circuits in series with each other, and wherein each of the two loop divide-by-2 circuits consists of a D flip-flop.

2. The divide-by-1.5 circuit of claim 1 , wherein the divide-by-3 circuit comprises:
a first D flip-flop having a non-inverted clock input coupled to a node defining the input of the divide-by-3 circuit;
a second D flip-flop having a non-inverted clock input coupled to the node defining the input of the divide-by-3 circuit and having an input coupled to an output of the first D flip-flop;
a third D flip-flop having an inverted clock input coupled to the node defining the input of the divide-by-3 circuit and having an input coupled to an output of the second D flip-flop;
a first NOR gate having a first input coupled to the output of the first D flip-flop, a second input coupled to the output of the second D-flip-flop, and an output coupled to a D input of the first D flip-flop; and
a second NOR gate having a first input coupled to an output of the third D flip-flop, a second input coupled to the output of the second D-flip-flop, and an output defining the output of the divide-by-3 circuit.

3. The divide-by-1.5 circuit of claim 1 , wherein the comparison circuit of the PLL circuitry comprises a phase-frequency detector (PFD).

4. The divide-by-1.5 circuit of claim 1 , wherein the VCO of the PLL circuitry comprises a ring VCO.

5. The divide-by-1.5 circuit of claim 4 , wherein the ring VCO of the PLL circuitry comprises a pair of cross-coupled inverters.

6. The divide-by-1.5 circuit of claim 1 , wherein the comparison circuit of the PLL circuitry comprises an exclusive-OR (XOR) gate.

7. The divide-by-1.5 circuit of claim 1 , wherein the loop filter of the PLL circuitry comprises a resistance and a capacitance.

8. A divide-by-1.5 circuit, comprising:
a divide-by-3 circuit having an input coupleable to a source of an input signal, the divide-by-3 circuit comprising: a first D flip-flop having a non-inverted clock input coupled to a node defining the input of the divide-by-3 circuit; a second D flip-flop having a non-inverted clock input coupled to the node defining the input of the divide-by-3 circuit and having an input coupled to an output of the first D flip-flop; a third D flip-flop having an inverted clock input coupled to the node defining the input of the divide-by-3 circuit and having an input coupled to an output of the second D flip-flop; a first NOR gate having a first input coupled to the output of the first D flip-flop, a second input coupled to the output of the second D-flip-flop, and an output coupled to a D input of the first D flip-flop; and a second NOR gate having a first input coupled to an output of the third D flip-flop, a second input coupled to the output of the second D-flip-flop, and an output defining the output of the divide-by-3 circuit; and
a frequency doubler circuit comprising phase-locked loop (PLL) circuitry, the frequency doubler circuit having an input coupled to an output of the divide-by-3 circuit and having an output defining an output of the divide-by-1.5 circuit, the PLL circuitry comprising a comparison circuit, a loop filter, a voltage-controlled oscillator (VCO), and a loop divider circuit, the comparison circuit having a first input defining the input of the frequency doubler circuit, the loop divider circuit having an input coupled to an output of the VCO and an output coupled to a second input of the comparison circuit, an output of the VCO defining an output of the frequency doubler circuit, the loop filter coupled to a node connected to an output of the comparison circuit and an input of the VCO, wherein the frequency doubler circuit comprises a pre-divide-by-2 circuit having an output coupled to the first input of the comparison circuit, the loop divider circuit including a loop divide-by-4 circuit having two loop divide-by-2 circuits in series with each other, and wherein each of the two loop divide-by-2 circuits consists of a D flip-flop.

9. The divide-by-1.5 circuit of claim 8 , wherein the comparison circuit of the PLL circuitry comprises a phase-frequency detector (PFD).

10. The divide-by-1.5 circuit of claim 8 , wherein the VCO of the PLL circuitry comprises a ring VCO.

11. The divide-by-1.5 circuit of claim 10 , wherein the ring VCO of the PLL circuitry comprises a pair of cross-coupled inverters.

12. The divide-by-1.5 circuit of claim 8 , wherein the comparison circuit of the PLL circuitry comprises an exclusive-OR (XOR) gate.

13. The divide-by-1.5 circuit of claim 8 , wherein the loop filter of the PLL circuitry comprises a resistance and a capacitance.

14. The divide-by-1.5 circuit of claim 1 , wherein the divide-by-1.5 circuit receives a time-varying signal having a frequency f and generates an output signal having a frequency f/1.5.

15. The divide-by-1.5 circuit of claim 1 , wherein the divide-by-1.5 circuit receives a time-varying signal and generates an output signal with a 50 percent duty cycle.

16. The divide-by-1.5 circuit of claim 1 , wherein the divide-by-3 circuit comprises a two-bit counter.

17. The divide-by-1.5 circuit of claim 16 , wherein the two-bit counter is responsive to a rising edge of a time-varying input signal.

18. The divide-by-1.5 circuit of claim 16 , wherein the two-bit counter generates a least significant bit and a most significant bit, and wherein the output of the divide-by-3 circuit represents a delayed version of the least significant bit.

19. The divide-by-1.5 circuit of claim 1 , wherein the comparison circuit is a phase-frequency detector.

20. The divide-by-1.5 circuit of claim 19 , wherein the comparison circuit includes elements fabricated using at least one complementary metal-oxide-semiconductor technology.

Assignees

• Avago Technologies General Ip

Inventors

• Atesoglu Ali

Classifications

• H03K23/505 Primary

  with a base which is an odd number · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title