By odd integer digital frequency divider circuit and method

Patent metadata

Field	Value
Publication number	US-10439618-B2
Application number	US-201816196426-A
Country	US
Kind code	B2
Filing date	Nov 20, 2018
Priority date	Dec 22, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

First claim

The invention claimed is:

1. A circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N, comprising:
a shift register comprising a number of N+1 clock gating cells being connected in series to each other and a shift logic,
wherein an input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells,
wherein the shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells;
a multiplexer configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal,
a frequency generator configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

2. The circuit according to claim 1 ,
wherein a gate enable input of each one the number of N+1 clock gating cells is connected to an enable signal output of the directly preceding one of the number of N+1 clock gating cells, wherein a respective enable signal is fed from the enable signal output of each clock gating cell to the gate enable input of the directly preceding clock gating cell.

3. The circuit according to claim 1 , further comprising:
a multiplexer control logic configured to receive the rotation clock signal and to control a selective connection of one of the input ports to the output of the multiplexer based on the rotation clock signal.

4. The circuit according to claim 1 , wherein the shift logic comprises:
an NOR gate configured to receive the enable signals and to logically combine the received enable signals to generate a combined enable signal; and
a gated latch configured to receive the combined enable signal at a data input and to receive the input clock signal at a clock signal input and to output the feedback signal an output.

5. The circuit according to claim 4 , further comprising:
wherein the set of the number of N+1 clock gating cells comprises N−3 clock gating cells first in sequence of the number of N+1 clock gating cells.

6. The circuit according to claim 4 , wherein the multiplexer control logic comprises:
a counter configured to detect an edge in the rotation clock signal and to cyclically count in response to an edge detection, wherein a counter value is supplied to the multiplexer as multiplexer selecting control signal, in response to which the multiplexer selectively connects a respective input port to the output.

7. The circuit according to claim 6 ,
wherein the counter is a cyclic counter.

8. The circuit according to claim 6 ,
wherein the counter is a Gray code counter.

9. The circuit according to claim 6 ,
wherein the counter is arranged to detect a falling edge of the rotation clock signal.

10. The circuit according to claim 6 ,
wherein the multiplexer control logic is arranged to control the multiplexer to cyclically connect the N+1 gated clock signals in reverse order according to the serial connection of the clock gating cells to the output.

11. The circuit according to claim 1 ,
wherein the frequency generator comprises a gated latch clocked by the rotation clock signal and having a feedback path connecting on inverted output to a data input,
wherein the output clock signal is present at an output of the gated latch.

12. The circuit according to claim 1 ,
wherein the gated clock signals have a frequency of

2

N
+
1

of the frequency of the input clock signal and a duty cycle factor

1

N
+
1

,

wherein the enable signals have a frequency of

2

N
+
1

of the frequency of the input clock signal and a duty cycle factor

2

N
+
1

.

13. The circuit according to claim 1 ,
wherein the input clock signal has a duty cycle of 50%.

14. A method of dividing a frequency of an input clock signal by odd integer N, comprising:
feeding an input clock signal into clock signal inputs of each one of a number of N+1 clock gating cells, wherein the N+1 clock gating cells are connected in series to each other in a shift register further comprising a shift logic;
receiving at the shift logic enable signals from a set of the number of N+1 clock gating cells generating a feedback signal;
supplying by the shift logic the feedback signal to a gate enable input of the first one of the number of N+1 clock gating cells;
receiving at a multiplexer from the number of N+1 clock gating cells N+1 gated clock signals;
outputting by the at a multiplexer a rotation clock signal, wherein the rotation clock signal has a frequency of 2/N of the frequency of the input clock signal;
receiving at a frequency generator; and
generating at the frequency generator an output clock signal having a frequency of 1/N.

15. The method of claim 14 , further comprising:
receiving at a multiplexer control logic the rotation clock signal and controlling by the multiplexer control logic a selective connection of one of the input ports to the output of the multiplexer based on the rotation clock signal.

Assignees

• Nxp Usa Inc

Inventors

• Robin Thierry
• Pechaud Bernard Pierre Francois
• Desposito Domenico

Classifications

• H03K23/505 Primary

  with a base which is an odd number · CPC title

• H03K23/005

  using minimum change code, e.g. Gray Code · CPC title

• H03K21/026

  comprising logic circuits · CPC title

• H03K21/40

  Monitoring; Error detection; Preventing or correcting improper counter operation · CPC title

• H03K21/08

  Output circuits · CPC title