Semiconductor die, semiconductor package and substrate dicing method
US-2024421000-A1 · Dec 19, 2024 · US
Fabrication method for a chip package
US9064950B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9064950-B2 |
| Application number | US-201314135506-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 19, 2013 |
| Priority date | Dec 1, 2009 |
| Publication date | Jun 23, 2015 |
| Grant date | Jun 23, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for forming a chip package, comprising: providing a semiconductor substrate covered by an intermetal dielectric layer, wherein the semiconductor substrate includes a plurality of device regions, a structural etching region, and a peripheral pad region spaced apart laterally, wherein the peripheral pad region contains a plurality of conducting pads; providing a chip protection layer covering the intermetal dielectric layer and the conducting pads;…
Assignees
Inventors
Classifications
- H10P54/00Primary
Electricity · mapped topic
Operations & Transport · mapped topic
Operations & Transport · mapped topic
Operations & Transport · mapped topic
- B81C1/00825Primary
Operations & Transport · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9064950B2 cover?
- An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching…
- Who is the assignee on this patent?
- Xintec Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 23 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).