Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Coreless multi-layer circuit substrate with minimized pad capacitance
US9060428B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9060428-B2 |
| Application number | US-201213612459-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 12, 2012 |
| Priority date | Mar 9, 2010 |
| Publication date | Jun 16, 2015 |
| Grant date | Jun 16, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A system comprising: a semiconductor chip; and a multilayer interconnecting substrate operatively connected to the semiconductor chip, wherein said multilayer interconnecting substrate includes a coreless multilayer stack; and a base that includes at least two metal layers oppositely placed relative to each other; at least one conductive element fabricated on each of the at least two metal layers; a first insulator having a first dielectric constant…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9060428B2 cover?
- A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two…
- Who is the assignee on this patent?
- Bills Kevin, Bohra Mahesh, Choi Jinwoo, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 16 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).