Selective cuts to remove predicted interconnect bulging regions
US-2024419882-A1 · Dec 19, 2024 · US
Method of generating a set of defect candidates for wafer
US9057965B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9057965-B2 |
| Application number | US-201213692396-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 3, 2012 |
| Priority date | Dec 3, 2012 |
| Publication date | Jun 16, 2015 |
| Grant date | Jun 16, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of generating a set of defect candidates for a wafer, the wafer comprising at least one die manufactured according to a mask, the mask being prepared by combining a plurality of layout areas, the method comprising: generating, by a hardware processor, a filtration area according to a graph operation of one or more of the plurality of layout areas, and the graph operation comprising at least expanding or shrinking the one or more of the plurality of…
Assignees
Inventors
Classifications
- G06F30/398Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G03F7/705Primary
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9057965B2 cover?
- A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting …
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G06F30/398. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 16 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).