Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Through silicon via keep out zone formation method and system
US9054166B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9054166-B2 |
| Application number | US-201314057951-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 18, 2013 |
| Priority date | Aug 31, 2011 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming an integrated circuit (IC), the method comprising: receiving a substrate having a plurality of active devices thereon; and forming a first through silicon via (TSV) such that none of the plurality of active devices are positioned in a first keep out zone (KOZ), the first KOZ being a region in which a stress impact of the first TSV exceeds a first threshold, the first KOZ having a first radius to a center of the first TSV in a first crys…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10W20/20Primary
Electricity · mapped topic
Electricity · mapped topic
- H10W42/121Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9054166B2 cover?
- Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performanc…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).