Semiconductor devices having a seal ring
US-2024413245-A1 · Dec 12, 2024 · US
Semiconductor structure and method of generating masks for making integrated circuit
US9053255B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9053255-B2 |
| Application number | US-201213650859-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 12, 2012 |
| Priority date | Oct 12, 2012 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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Abstract
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A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of generating masks for making an integrated circuit, the masks comprising layout patterns corresponding to first and second groups of conductive paths of the integrated circuit, and the method comprising: determining, by a hardware processor, if a coupling capacitance value of a conductive path of the first and second groups of conductive paths is greater than a predetermined threshold value, the determination being performed based on at least a re…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/43Primary
Electricity · mapped topic
Physics · mapped topic
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- What does patent US9053255B2 cover?
- A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined le…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W20/43. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 09 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).