Programmable equalization with compensated impedance

Patent metadata

Field	Value
Publication number	US-9048824-B2
Application number	US-201213712574-A
Country	US
Kind code	B2
Filing date	Dec 12, 2012
Priority date	Dec 12, 2012
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

Described is a chip comprising: a pull-up driver with a first impedance, the pull-up driver coupled to a node; a pull-down driver with a second impedance, the pull-down driver coupled to the node; and an equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant.

First claim

The invention claimed is:

1. A method, comprising:
for a driver comprising a plurality of parallel transistor segments each comprised of a pull-up transistor and a pull-down transistor, where, a percentage of the parallel transistor segments impose logic-low de-emphasis by having a respective pull-up transistor enabled while said driver is driving a logic level low with a respective pull-down transistor of the other transistor segments and impose logic-high de-emphasis by having a…

Assignees

• Intel Corp

Inventors

• Chan Hong H
• Strayer Jayson D
• Hua My M

Classifications

• G11C7/1051

  Physics · mapped topic

• G11C7/1048

  Physics · mapped topic

• H03K19/0005 Primary

  Electricity · mapped topic

• H04L25/0278

  Electricity · mapped topic

• H04L25/0298

  Electricity · mapped topic