Field effect transistor having semiconductor operating layer formed with an inclined side wall

Patent metadata

Field	Value
Publication number	US-9048302-B2
Application number	US-31877909-A
Country	US
Kind code	B2
Filing date	Jan 8, 2009
Priority date	Jan 11, 2008
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess; a gate electrode formed on the insulating layer at the recess; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess in between and electrically connected to the semiconductor operating layer. The recess includes a side wall inclined relative to the semiconductor operating layer.

First claim

What is claimed is:

1. A field effect transistor, comprising:
a substrate;
a lower semiconductor layer of nitride-based compound semiconductor formed on the substrate;
a semiconductor operating layer of nitride-based compound semiconductor formed on the lower semiconductor layer and having a recess, the semiconductor operating layer comprising a carrier drifting layer formed on the lower semiconductor layer and a carrier supplying layer formed on the carrier drifting layer, the carrier supplying layer having a band gap energy greater than that of the carrier drifting layer;
an insulating layer formed on the semiconductor operating layer and contacting the lower semiconductor layer at a bottom of the recess;
a gate electrode formed on the insulating layer at the recess; and
a source electrode and a drain electrode formed on the same surface of the semiconductor operating layer and electrically connected to the semiconductor operating layer with the recess in between the source electrode and the drain electrode, wherein
a side wall of the recess at a side of the drain electrode ascends at an angle of θ1 from a top surface of the lower semiconductor layer,
a side wall of the recess at a side of the source electrode ascends vertically or at an angle of θ2 from the top surface of the lower semiconductor layer, and
the angle θ1 is different from the angle θ2.

2. The field effect transistor according to claim 1 , wherein
the lower semiconductor layer has a p type electrical conductivity, and
the carrier drifting layer has an n type electrical conductivity.

3. The field effect transistor according to claim 2 , wherein
the side wall of the recess at the side of the source electrode ascends at the angle θ2 from the top surface of the lower semiconductor layer, and
each of the angles θ1 and θ2 is smaller than 65 degrees.

4. The field effect transistor according to claim 2 , wherein
the recess extends into a partial thickness of the lower semiconductor layer, and
the insulating layer contacts the lower semiconductor layer not only at the bottom of the recess but also at the side walls.

5. The field effect transistor according to claim 2 , wherein the side walls of the recess in the semiconductor operating layer are curved.

6. The field effect transistor according to claim 2 , further comprising a pair of contact regions contacting with the source electrode and the drain electrode, respectively, wherein
the contact regions have a conductivity higher than that of the semiconductor operating layer, and
each of the contact regions extends, in a thickness direction of the substrate, from the respective source or drain electrode to the lower semiconductor layer.

7. The field effect transistor according to claim 2 , further comprising a pair of contact regions contacting with the source electrode and the drain electrode, respectively, wherein
the contact regions have a conductivity higher than that of the semiconductor operating layer, and
each of the contact regions extends, in a thickness direction of the substrate, from the respective source or drain electrode into a partial thickness of the lower semiconductor layer.

8. The field effect transistor according to claim 2 , wherein
the lower semiconductor layer is a p type GaN, and
the carrier drifting layer is an n-type GaN.

9. The field effect transistor according to claim 1 , wherein
the lower semiconductor layer has a p-type electrical conductivity,
the carrier drifting layer is a un-doped semiconductor layer,
the carrier supplying layer has an n− type electrical conductivity
the semiconductor operating layer further includes a pair of contact regions respectively contacting with the source electrode and the drain electrode, and
the contact regions have an n+ type electrical conductivity.

10. The field effect transistor according to claim 1 , wherein
the side wall of the recess at the side of the source electrode ascends at the angle θ2 from the top surface of the lower semiconductor layer, and
each of the angles θ1 and θ2 is smaller than 65 degrees.

11. The field effect transistor according to claim 2 , wherein an entirety of the insulating layer is above the top surface of the lower semiconductor layer.

12. The field effect transistor according to claim 2 , wherein the recess exposes the top surface of the lower semiconductor layer and the semiconductor operating layer is on the exposed top surface.

13. The field effect transistor according to claim 2 , wherein a bottom surface of the semiconductor operating layer is coplanar with the bottom surface of the insulating layer.

14. The field effect transistor according to claim 1 , wherein an entirety of the insulating layer is above the top surface of the lower semiconductor layer.

15. The field effect transistor according to claim 1 , wherein the recess exposes the top surface of the lower semiconductor layer and the operating layer is on the exposed top surface.

16. The field effect transistor according to claim 1 , wherein a bottom surface of the operating layer is coplanar with the bottom surface of the insulating layer.

17. The field effect transistor according to claim 2 , wherein
the side wall of the recess at the side of the source electrode ascends at the angle θ2 from the top surface of the lower semiconductor layer, and
each of the angles θ1 and θ2 is greater than 45 degrees and smaller than 75 degrees.

18. The field effect transistor according to claim 2 , wherein the side wall of the recess at the side of the source electrode ascends vertically from the top surface of the lower semiconductor layer.

19. The field effect transistor according to claim 1 , wherein
the side wall of the recess at the side of the source electrode ascends at the angle θ2 from the top surface of the lower semiconductor layer, and
each of the angles θ1 and θ2 is greater than 45 degrees and smaller than 75 degrees.

20. The field effect transistor according to claim 1 , wherein the side wall of the recess at the side of the source electrode ascends vertically from the top surface of the lower semiconductor layer.

Assignees

• Sato Yoshihiro
• Kambayashi Hiroshi
• Niiyama Yuki
• Nomura Takehiko
• Yoshida Seikoh
• Iwami Masayuki
• Li Jiang
• Furukawa Electric Co Ltd

Inventors

• Sato Yoshihiro
• Kambayashi Hiroshi
• Niiyama Yuki
• Nomura Takehiko
• Yoshida Seikoh
• Iwami Masayuki
• Li Jiang

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title