Packaged semiconductor devices and packaging methods

Patent metadata

Field	Value
Publication number	US-9035461-B2
Application number	US-201313754518-A
Country	US
Kind code	B2
Filing date	Jan 30, 2013
Priority date	Jan 30, 2013
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.

First claim

What is claimed is:

1. A method of packaging a semiconductor device, the method comprising:
forming a plurality of through-vias over a carrier;
coupling an integrated circuit die to the carrier;
forming a first redistribution layer (RDL) over a first side of the plurality of through-vias and the integrated circuit die;
removing the carrier;
forming a second RDL over a second side of the plurality of through-vias and the integrated circuit die, the second RDL being formed i…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hu Yen-Chang
• Hsiao Ching-Wen
• Chen Chen-Shien

Classifications

• H10W90/736

  Electricity · mapped topic

• H10W90/724

  Electricity · mapped topic

• H10W90/297

  Electricity · mapped topic

• H10W74/142

  Electricity · mapped topic

• H10W74/00

  Electricity · mapped topic