Methods of forming a semiconductor device

Patent metadata

Field	Value
Publication number	US-9034765-B2
Application number	US-201313956556-A
Country	US
Kind code	B2
Filing date	Aug 1, 2013
Priority date	Aug 27, 2012
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
forming first preliminary holes over an etch target layer, the first preliminary holes arranged as a plurality of rows in a first direction;
forming dielectric patterns each filling one of the first preliminary holes;
sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns;
forming etch control patterns between the dielectric patterns;
forming second preliminary h…

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Joonsoo
• Seo Jungwoo
• Yoon Kyoungryul
• Kim Cheolhong
• Nam Seokwoo
• Park Yongjik

Classifications

• H10P76/4085 Primary

  Electricity · mapped topic

• H10P50/00 Primary

  Electricity · mapped topic

• H01L21/302 Primary

  Electricity · mapped topic

• H10P76/204

  Electricity · mapped topic