Photolithography alignment mark, mask and semiconductor wafer containing the same mark

Patent metadata

Field	Value
Publication number	US-9024456-B2
Application number	US-201113329152-A
Country	US
Kind code	B2
Filing date	Dec 16, 2011
Priority date	Sep 23, 2011
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer.

First claim

What is claimed is:

1. A semiconductor wafer, comprising:
a plurality of wafer layers, each of the wafer layers comprising:
a primary wafer region for forming a required circuit pattern; and
a mark region for accommodating one or more photolithography alignment marks,

wherein the photolithography alignment marks comprise:
a plurality of first alignment lines arranged in parallel with each other in a first direction;
a plurality of second alignment lines arranged in parallel with each other in a second direction perpendicular to the first direction,

wherein each first alignment line in the plurality of the first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each second alignment line in the plurality of the second alignment lines is composed of the predetermined number of second fine alignment lines uniformly spaced from each other,
wherein the photolithography alignment marks are positioned in the mark regions of one or more selected layers among the plurality of wafer layers.

2. The semiconductor wafer of claim 1 , wherein the predetermined number is the same and is 3.

3. The semiconductor wafer according to claim 1 , wherein the predetermined number is the same and is 2.

4. The semiconductor according to claim 1 , wherein the predetermined number is the same and is 4.

5. The semiconductor wafer according to claim 1 , wherein a width of the first fine alignment line is equal to a width of a space between any two adjacent first fine alignment lines, and a width of the second fine alignment line is equal to a width of a space between any two adjacent second fine alignment lines.

6. The semiconductor wafer of claim 5 , wherein the width of the first alignment line is 8 μm, and the width of the second alignment line is 8 μm.

7. The semiconductor wafer according to claim 1 , wherein the plurality of the first alignment lines are spaced uniformly, and the plurality of second alignment lines are spaced uniformly.

8. The semiconductor wafer of claim 7 , wherein the width of the space between any two adjacent first alignment lines is equal to the width of the space between any two adjacent second alignment lines.

9. The semiconductor wafer of claim 8 , wherein both of the space between any two adjacent first alignment lines and the space between any two adjacent second alignment lines have a width of 8 μm or 9.6 μm.

10. The semiconductor wafer of claim 7 , wherein the space between any two adjacent first alignment lines has a width different from that of the space between any two adjacent second alignment lines.

11. The semiconductor wafer of claim 10 , wherein the spaces between a first of either of the adjacent first alignment lines or the second alignment lines has the width of 8 μm and the spaces between the other of the first or second alignment line has a width of 9.6 μm.

12. The semiconductor wafer according to claim 1 , wherein the plurality of the first alignment lines is grouped into first and second sets, wherein the first alignment lines in each set are spaced uniformly, and the space between any two adjacent first alignment lines in the first set has a width different from that of the space between any two adjacent first alignment lines in the second set.

13. The semiconductor wafer of claim 12 , wherein the spaces between a first of either of the adjacent first alignment lines or the second alignment lines has the width of 8 μm and the spaces between the other of the first or second alignment line has a width of 9.6 μm.

14. The semiconductor wafer according to claim 1 , wherein, the plurality of the second alignment lines is grouped into first and second sets, wherein the second alignment lines in each set are spaced uniformly, and the space between any two adjacent second alignment lines in the first set has a width different from that of the space between any two adjacent second alignment lines in the second set.

15. The semiconductor wafer of claim 14 , wherein the spaces between a first of either of the adjacent first alignment lines or the second alignment lines has the width of 8 μm and the spaces between the other of the first or second alignment line has a width of 9.6 μm.

16. The semiconductor wafer according to claim 1 , wherein the first fine alignment lines and the second fine alignment lines are made of a metal, and the space between any two adjacent first fine alignment lines and the space between any two adjacent second fine alignment lines are made of an oxide, and the space between any two adjacent first alignment lines and the space between any two adjacent second alignment lines is made of an oxide.

17. The semiconductor wafer according to claim 1 , wherein the first fine alignment lines and the second fine alignment lines are made of an oxide, and the space between any two adjacent first fine alignment lines and the space between any two adjacent second fine alignment lines are made of a metal, and the space between any two adjacent first alignment lines and the space between any two adjacent second alignment lines is made of metal.

18. The semiconductor wafer of claim 1 , wherein the mark region is located in one or more corners of the wafer layer.

19. The semiconductor wafer of claim 18 , wherein the mark region comprises a plurality of mark sub-regions, each of which can receive one or more said photolithography alignment marks, at least two corners of the wafer layer each having a mark sub-region provided therein.

20. The semiconductor wafer of claim 19 , wherein the mark region comprises a first mark sub-region and a second mark sub-region, the first mark sub-region and the second mark sub-region located in a lower-left corner and a upper-right corner of the wafer layer, respectively.

21. The semiconductor wafer of claim 19 , wherein the mark region comprises a first mark sub-region and a second mark sub-region, the first mark sub-region and the second mark sub-region located in a lower-right corner and a upper-left corner of the wafer layer, respectively.

22. The semiconductor wafer of claim 1 , wherein the plurality of wafer layers comprise one or more metal layers, and the photolithography alignment mark is formed in one or more of the mark regions of the one or more metal layers.

23. The semiconductor wafer of claim 22 , wherein the plurality of wafer layers further comprise an active area layer, a poly-Si gate layer, a contact layer and a passivation layer, the photolithography alignment marks being formed in the mark regions of the active area layer, the contact layer and the passivation layer.

24. The semiconductor wafer of claim 23 , wherein the photolithography alignment mark is also formed in the mark region of the poly-Si gate layer.

25. The semiconductor wafer according to claim 1 , wherein the photolithography alignment marks in the mark regions of the selected of the plurality of layers are staggered.

26. The semiconductor wafer of claim 25 , wherein the positions of the photolithography alignment marks in adjacent selected layers are separated by 1mm.

27. The semiconductor wafer of claim 1 , wherein the plurality of wafer layers first photolithography alignment marks and the second photolithography alignment marks which alternate, on a layer-by-layer basis, are formed in the mark regions of the selected layers, and the positions of the photolithography alignmen

Assignees

• Yang Xiaosong
• Yan Yibo
• Lu Tzu Hsuan
• Semiconductor Mfg Int Beijing

Inventors

• Yang Xiaosong
• Yan Yibo
• Lu Tzu Hsuan

Classifications

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L2223/5442

  Electricity · mapped topic