Embedded planar source/drain stressors for a finFET including a plurality of fins

Patent metadata

Field	Value
Publication number	US-9024355-B2
Application number	US-201213483200-A
Country	US
Kind code	B2
Filing date	May 30, 2012
Priority date	May 30, 2012
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a fin-containing semiconductor portion that includes a plurality of semiconductor fins, a first end portion, and a second end portion, each of said plurality of semiconductor fins, said first end portion, and said second end portion comprising a first semiconductor material, wherein each semiconductor fin among said plurality of semiconductor fins extends along a lengthwise direction and is laterally spaced from one another along a widthwise direction perpendicular to said lengthwise direction, and one end of each of said plurality of semiconductor fins is longitudinally adjoined to said first end portion and another end of each of said plurality of semiconductor fins is longitudinally adjoined to said second end portion, wherein each of said first end portion and said second end portion includes a proximal portion having a topmost surface that has a same height as a topmost surface of each of said plurality of semiconductor fins, and includes a distal portion having a topmost surface that has a lesser height than said topmost surface of each of said plurality of semiconductor fins, said proximal portion of each of said first end portion and said second end portion adjacent to said plurality of semiconductor fins;
a first stress-generating semiconductor portion in contact with said distal portion of said first end portion and an outer sidewall of said proximal portion of said first end portion and comprising a second semiconductor material having a different lattice constant than said first semiconductor material and epitaxially aligned to said first end portion; and
a second stress-generating semiconductor portion in contact with said distal portion of said second end portion and an outer sidewall of said proximal portion of said second end portion and comprising said second semiconductor material and epitaxially aligned to said second end portion.

2. The semiconductor structure of claim 1 , wherein said first stress-generating semiconductor portion is in contact with an entirety of a top surface of said distal portion of said first end portion and a sidewall surface of said first end portion, and said second stress-generating semiconductor portion is in contact with an entirety of a top surface of said distal portion of said second end portion and a sidewall surface of said second end portion.

3. The semiconductor structure of claim 1 , further comprising a buried insulator layer comprising a dielectric material and having a planar top surface, wherein an entirety of a bottom surface of said fin-containing semiconductor portion laterally extending from a sidewall surface of said distal portion of said first end portion to a sidewall surface of said distal portion of said second end portion is in contact with said planar top surface.

4. The semiconductor structure of claim 1 , further comprising a gate dielectric in contact with a lengthwise sidewall of said plurality of semiconductor fins.

5. The semiconductor structure of claim 4 , further comprising a gate electrode overlying said plurality of semiconductor fins and in contact with said gate dielectric.

6. The semiconductor structure of claim 1 , wherein an entire top surface of said first stress-generating semiconductor portion and an entire top surface of said second stress-generating semiconductor portion are within a same horizontal plane.

7. The semiconductor structure of claim 1 , further comprising:
a first gate spacer portion overlying said proximal portion of said first end portion and having a same thickness as a lateral extent of said proximal portion of said first end portion along said lengthwise direction of said plurality of semiconductor fins; and
a second gate spacer portion overlying said proximal portion of said second end portion and having a same thickness as a lateral extent of said proximal portion of said second end portion along said lengthwise direction of said plurality of semiconductor fins.

8. The semiconductor structure of claim 1 , further comprising a plurality of fin-defining mask structures overlying said plurality of semiconductor fins, said plurality of semiconductor fins has a same width as said plurality of fin-defining mask structures.

9. The semiconductor structure of claim 8 , wherein said plurality of fin-defining mask structures comprises a dielectric material.

10. The semiconductor structure of claim 8 , wherein said first stress-generating semiconductor portion is in contact with a sidewall of each of said plurality of fin-defining mask structures, and said second stress-generating semiconductor portion is in contact with another sidewall of each of said plurality of fin-defining mask structures.

11. The semiconductor structure of claim 1 , wherein said topmost surfaces of said proximal portions are surfaces of said first semiconductor material, and said topmost surfaces of said distal portions are additional surfaces of said first semiconductor material.

12. The semiconductor structure of claim 1 , wherein said fin-containing semiconductor portion consists of said first semiconductor material and electrical dopant atoms.

13. The semiconductor structure of claim 1 , wherein an entire bottom surface of said fin-containing semiconductor portion bounded by a periphery adjoining sidewalls of said fin-containing semiconductor portion is within a horizontal plane.

14. The semiconductor structure of claim 1 , wherein said topmost surfaces of said distal portions are interfaces with bottom surfaces of said first stress-generating semiconductor portion and said second stress-generating semiconductor portion.

15. The semiconductor structure of claim 7 , wherein an outer sidewall of said first gate spacer portion is vertically coincident with said sidewall of said proximal portion of said first end portion, and an outer sidewall of said second gate spacer portion is vertically coincident with said sidewall of said proximal portion of said second end portion.

16. The semiconductor structure of claim 1 , wherein an entire bottom surface of said fin-containing semiconductor portion is within a horizontal plane, and said fin-containing semiconductor portion consists of a first region having a first height and two second regions having a second height that is less than said first height, wherein said first region consists of said plurality of semiconductor fins, said proximal portion of said first end portion, and said proximal portion of said second end portion.

17. The semiconductor structure of claim 16 , wherein said second region consists of said distal portion of said first end portion and said distal portion of said second end portion.

18. The semiconductor structure of claim 1 , wherein said first stress-generating semiconductor portion is in contact with a sidewall of said distal portion of said first end portion, and said second stress-generating semiconductor portion is in contact with a sidewall of said distal portion of said second end portion.

19. The semiconductor structure of claim 18 , wherein said sidewall of said distal portion of said first end portion is more distal than said plurality of semiconductor fins than said sidewall of said proximal portion of said first end portion.

20. The semiconductor structure of claim 8 , wherein each sidewall of said plurality of fin-defining mask structures is vertically coincident with a corresponding outer sidewall of said first gate spacer portion and said second gate spacer portion.

Assignees

• Chang Josephine B
• Chang Paul
• Guillorn Michael A
• Sleight Jeffrey W
• IBM

Inventors

• Chang Josephine B
• Chang Paul
• Guillorn Michael A
• Sleight Jeffrey W

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title