Top corner rounding by implant-enhanced wet etching

Patent metadata

Field	Value
Publication number	US-9023709-B2
Application number	US-201314011413-A
Country	US
Kind code	B2
Filing date	Aug 27, 2013
Priority date	Aug 27, 2013
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

When forming metallization layers of advanced semiconductor devices, one often has to fill apertures with a high aspect ratio with a metal, such as copper. The present disclosure provides a convenient method for forming apertures with a high aspect ratio in an insulating layer. This insulating layer may have been deposited on the surface of a semiconductor device. The proposed method relies on an ion implantation step performed on the insulating layer, followed by an etch, which is preferably a wet etch.

First claim

What is claimed:

1. A method, comprising:
forming a transistor structure comprising a gate electrode, a source region and a drain region in and above a semiconductor layer;
forming an insulating layer above the surface of said semiconductor layer after forming said transistor structure;
performing a first etch process in order to form at least one opening in a predetermined portion of said insulating layer;
performing an ion implantation so as to implant impurity ions into an upper portion of said insulating layer; and
performing a second etch process so as to remove at least a portion of said insulating layer comprising the implanted impurity ions after performing said ion implantation;
wherein during said second etch process said upper portion of said insulating layer comprising the implanted impurity ions is etched at a different rate from the remaining portion of said insulating layer.

2. The method of claim 1 , wherein said second etch process is such that the etch rate of said insulating layer is higher in the portion of the insulating layer comprising the implanted impurity ions and lower in areas of the insulating layer not containing the implanted impurity ions.

3. The method of claim 1 , wherein said transistor is part of a semiconductor device that comprises at least a residual portion of said insulating layer after performing said second etch.

4. The method of claim 1 , wherein said second etch process comprises a wet etch.

5. The method of claim 1 , wherein said second etch process comprises treating said semiconductor device with a solution containing at least one of hydrofluoric acid (HF) and ammonium hydroxide (NH 4 OH).

6. The method of claim 1 , wherein said second etch process results in an upper portion of said opening being wider than a width of a remaining portion of said aperture.

7. The method of claim 1 , wherein said impurity ions implanted by performing said ion implantation comprise germanium or nitrogen ions.

8. The method of claim 1 , wherein said ion implantation is performed at a beam energy in the range of about 1 to about 10 keV.

9. The method of claim 1 , wherein said ion implantation is performed at a dose of about 10 13 to 10 14 cm −2 .

10. The method of claim 1 , wherein the direction of the ion beam used for performing said implantation forms an angle different from zero with the normal direction to the surface of said semiconductor layer.

11. The method of claim 1 , wherein said ion implantation comprises at least a first ion implantation performed with an ion beam directed along a first direction and a second ion implantation performed with an ion beam directed along a second direction, said first and second direction having different azimuth angles, given a longitudinal axis parallel to the normal direction to the surface of said semiconductor layer.

12. The method of claim 1 , wherein said ion implantation is performed after said first etch process.

13. The method of claim 1 , wherein said first etch process comprises an anisotropic etch.

14. The method of claim 1 , wherein said at least one opening exposes a predetermined portion of the surface of said transistor structure.

15. The method of claim 1 , further comprising, after performing said second etch process, depositing a metal so as to fill said at least one opening with said metal.

16. The method of claim 15 , wherein said deposition comprises an electrochemical technique.

17. The method of claim 15 , wherein said deposited metal comprises copper or tungsten.

18. The method of claim 15 further comprising performing a surface polishing process so as to remove at least a surface portion of said metal.

19. A method, comprising:
forming a transistor structure comprising a gate electrode, a source region and a drain region in and above a semiconductor layer;
forming an insulating layer above the surface of said semiconductor layer after forming said transistor structure;
performing a first anisotropic etch process in order to form at least one opening in a predetermined portion of said insulating layer;
performing an angled ion implantation process so as to implant impurity ions into an upper portion of said insulating layer adjacent said opening; and
performing a second etch process so as to remove at least a portion of said insulating layer comprising the implanted impurity ions after performing said angled ion implantation, wherein said second etch process results in an upper portion of said opening being wider than a width of a remaining portion of said aperture.

20. The method of claim 19 , wherein during said second etch process said upper portion of said insulating layer comprising the implanted impurity ions is etched at a different rate from the remaining portion of said insulating layer.

21. The method of claim 19 , wherein said second etch process is such that the etch rate of said insulating layer is higher in the portion of the insulating layer comprising the implanted impurity ions and lower in areas of the insulating layer not containing the implanted impurity ions.

22. The method of claim 19 , wherein said second etch process comprises a wet etch process.

Assignees

• Globalfoundries Inc

Inventors

• Moll Hans-Peter
• Lepper Marco
• Graf Werner

Classifications

• H10P30/40

  into insulating materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/095

  by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title