Semiconductor device with aligned bumps

Patent metadata

Field	Value
Publication number	US-9018969-B2
Application number	US-201213608138-A
Country	US
Kind code	B2
Filing date	Sep 10, 2012
Priority date	Sep 27, 2011
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip including a first plurality of first bumps on a first surface and a plurality of first wirings; and
a second chip including a plurality of second bumps and a plurality of second wirings, and being stacked with the first chip such that each of the plurality of second bumps is coupled to a corresponding one of the first plurality of first bumps of the first chip;
wherein the first wirings, the first bumps, th…

Assignees

• Ishikawa Toru
• Segawa Machio
• Ps4 Luxco Sarl

Inventors

• Ishikawa Toru
• Segawa Machio

Classifications

• G11C29/025 Primary

  Physics · mapped topic

• H10W90/752

  Electricity · mapped topic

• H10W90/722

  Electricity · mapped topic

• H10W72/07251

  Electricity · mapped topic

• H10W72/20

  Electricity · mapped topic