Adaptable datapath for a digital processing system

Patent metadata

Field	Value
Publication number	US-9015352-B2
Application number	US-201414230529-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 22, 2001
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

First claim

What is claimed is:

1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:
a functional unit configured to perform a digital operation;
one or more multiplexers coupled to the memory bus;
a configurable data path configurably coupled to the one or more multiplexers and the functional unit, the configurable data path configured in response to a first configuration information to provide a…

Assignees

• Altera Corp

Inventors

• Ramchandran Amit

Classifications

• G06F13/16

  Physics · mapped topic

• G06F9/3826

  Physics · mapped topic

• G06F9/30014 Primary

  Physics · mapped topic

• G06F9/3012

  Physics · mapped topic

• G06F9/3824

  Physics · mapped topic