Bi-phase communication demodulation techniques

Patent metadata

Field	Value
Publication number	US-9014305-B2
Application number	US-201113337674-A
Country	US
Kind code	B2
Filing date	Dec 27, 2011
Priority date	Jun 23, 2011
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.

First claim

What is claimed is:

1. A bi-phase communication receiver system comprising:
an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal;
a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples; and
a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output, wherein the digital filter is configured as a finite impulse response (FIR) filter comprising a set of tap weights comprising values associated with at least one period of the preamble of the bi-phase modulation signal and the set of tap weights are arranged in an alternating pattern of a plurality of first values of positive one and a respective plurality of second values of negative one, wherein each of the first and second values correspond to a respective one of the digital samples that are incrementally shifted into the FIR filter.

2. The system of claim 1 , wherein the FIR filter is configured to evaluate the digital samples to generate the output by, at each iteration, adding a respective tap weight product of a new digital sample shifted into the FIR filter, subtracting a respective tap weight product of a last digital sample shifted out of the FIR filter, and one of adding and subtracting respective tap weight products of digital samples shifted to respective filter taps associated with logic transitions of the preamble of the bi-phase modulation signal, with respect to an immediately preceding value of the output.

3. The system of claim 1 , wherein the preamble detector further comprises a preamble comparator configured to compare the output of the digital filter with a threshold, the period of the preamble of the bi-phase modulation signal being detected in response to the preamble comparator determining that the output of the digital filter is greater than the threshold.

4. The system of claim 3 , wherein the preamble detector further comprises a threshold generator configured to generate the threshold as having a moving average based on the amplitude of the digital samples.

5. A wireless power system comprising the bi-phase communication receiver system of claim 1 , the wireless power system comprising:
a wireless charger comprising a receiver configured to monitor a primary current associated with a primary inductor, the receiver comprising the bi-phase communication receiver system of claim 1 ; and
a portable electronic device comprising a transmitter configured to modulate the bi-phase communication signal onto a secondary current associated with a secondary inductor, the primary inductor and secondary inductor collectively forming an isolation transformer configured to transfer energy from the primary inductor to the secondary inductor to generate a voltage in the portable electronic device.

6. A bi-phase communication receiver system comprising:
an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal;
a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples; and
a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output wherein the digital filter is configured as a two-stage filter comprising a first digital filter and a second digital filter, the second digital filter being configured to sample the output of the first digital filter to amplify and further filter the output of the first digital filter to substantially compensate for noise associated with the bi-phase modulation signal, and wherein the first and second digital filters are configured as finite impulse response (FIR) filters, wherein the first digital filter comprises a set of tap weights comprising values associated with at least one period of the preamble of the bi-phase modulation signal, and wherein the second digital filter comprises a set of tap weights comprising non-zero values associated with taps at each of alternating logic transitions and zero values associated with remaining taps.

7. A bi-phase communication receiver system comprising:
an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal;
a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples; and
a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output, wherein the output of the digital filter has peak maxima corresponding to alignment of the period of the preamble of the bi-phase modulation signal with preprogrammed filter taps associated with the digital filter, and wherein the preamble detector comprises a synchronization controller configured to detect the peak maxima and to count the digital samples between each of a plurality of consecutive peak maxima to detect a clock frequency mismatch between the bi-phase communication receiver system and an associated transmitter, the peak detector being configured to adjust a sampling rate of the ADC based on the detected mismatch.

8. The system of claim 7 , wherein the synchronization controller comprises a proportional/integral loop controller configured to generate a signal indicative of an amount of adjustment to the sampling rate of the ADC proportional to a magnitude of the detected mismatch to adjust the sampling rate of the ADC to converge on a clock frequency of the associated transmitter.

9. A bi-phase communication receiver system comprising:
an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal;
a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples; and
a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output, wherein the bi-phase modulation signal comprises a first bi-phase modulation channel and a second bi-phase modulation channel, the bi-phase communication receiver system further comprising a channel selection controller configured to select one of the first and second bi-phase modulation channels for decoding by the bi-phase signal decoder based on a relative signal amplitude of the first and second bi-phase modulation channels, the channel selection controller being further configured to discard the other of the first and second bi-phase modulation channels in response to the selection.

10. The system of claim 9 , wherein the preamble detector comprises the channel selection controller, wherein the digital filter comprises a first digital filter associated with the first bi-phase modulation channel and a second digital filter associated with the first bi-phase modulation channel, the channel selection controller comprising a channel comparator configured to compare an output of the first digital filter with an output of the second digital filter to select the one of the first and second bi-phase modulation channels.

11. The system of claim 10 , wherein the preamble detec

Assignees

• Oettinger Eric Gregory
• Texas Instruments Inc

Inventors

• Oettinger Eric Gregory

Classifications

• H04L25/4904 Primary

  using self-synchronising codes, e.g. split-phase codes · CPC title

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• H04L7/046

  using a dotting sequence · CPC title

• H02J50/10

  using inductive coupling · CPC title

• H04L27/22

  Demodulator circuits; Receiver circuits · CPC title