Apparatus and method of receiver architecture and low-complexity decoder for line-coded and amplitude-modulated signal

Patent metadata

Field	Value
Publication number	US-9143200-B2
Application number	US-201313786709-A
Country	US
Kind code	B2
Filing date	Mar 6, 2013
Priority date	Sep 26, 2012
Publication date	Sep 22, 2015
Grant date	Sep 22, 2015

Abstract

In some examples, the receiver apparatus includes a receiver interface configured to receive a signal from a transmitter and output an input sequence of M-bit samples. The apparatus may also include a quantizer circuit configured to convert the input sequence of M-bit samples into an output sequence of N-bit samples, wherein M and N are positive integer numbers, and wherein M is greater than N. The apparatus may further include a decoder circuit configured to decode the output sequence of N-bit samples.

First claim

What is claimed is:

1. A receiver apparatus, comprising:
a receiver interface configured to receive a signal from a transmitter and output an input sequence of M-bit samples;
a quantizer circuit configured to convert the input sequence of M-bit samples into an output sequence of N-bit samples, wherein M and N are positive integer numbers greater than zero, and wherein M is greater than N;
a first circuit configured to generate bit boundary information for the output sequence of N-bit samples; and
a decoder circuit configured to decode the output sequence of N-bit samples, wherein the decoder circuit comprises:
a second circuit configured to select a group of the output sequence of N-bit samples based on the bit boundary information; and
a third circuit configured to decode the selected group of samples.

2. The apparatus of claim 1 , wherein M is 3 or greater, and wherein N is 1.

3. The apparatus of claim 1 , wherein M is 3 or greater, and wherein N is 2.

4. The apparatus of claim 1 , wherein the quantizer circuit is further configured to remove a time-varying DC direct current component from the input sequence of M-bit samples.

5. The apparatus of claim 1 , wherein the second circuit comprises:
a delay line configured to sequentially delay the output sequence of N-bit samples so as to select the group of samples; and
a sum block configured to calculate a weighted sum of the selected group of samples.

6. The apparatus of claim 5 , wherein the sum block is further configured to calculate the weighted sum using the following equation:

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where x[k], k=0, 1, . . . , N B −1, denotes the output sequence of N-bit samples, p[k] represents the probability of error at an index k, A={k|x[k]=a[k]}, B={k|x[k]=b[k]}, a[k] and b[k] denote two ideal quantizer output sequences corresponding to bit 0 and bit 1 , respectively, and Q [Y] means a quantized value (0 or 1) of Y.

7. The apparatus of claim 1 , wherein the second circuit comprises an accumulator configured to calculate a weighted accumul

Assignees

• Qualcomm Inc

Inventors

• Kang Eunmo

Classifications

• H04B5/266

  One coil at each side, e.g. with primary and secondary coils · CPC title

• H04B5/45

  Transponders · CPC title

• H04B5/0062

  Electricity · mapped topic

• H04B1/06

  Receivers · CPC title

• H04B5/0031

  Electricity · mapped topic