3-D integrated package

Patent metadata

Field	Value
Publication number	US-9013891-B2
Application number	US-201213417103-A
Country	US
Kind code	B2
Filing date	Mar 9, 2012
Priority date	Mar 9, 2012
Publication date	Apr 21, 2015
Grant date	Apr 21, 2015

Abstract

An electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.

First claim

What is claimed is:

1. An electronics package comprising:
a multilayer vertical transition, the multilayer vertical transition including:
a plurality of transition layers, each transition layer of the plurality of transition layers including:
an insulating layer;
a signal via, wherein:
the signal via passes through the insulating layer; and
the signal via is electrically coupled with the signal via of an adjacent transition layer;

a ground plane disposed at a face of the insulating layer, the ground plane including a signal cut, wherein the signal cut provides clearance between the ground plane and the signal via; and
a plurality of ground vias, wherein the ground vias are configured to electrically couple the ground plane of the transition layer with the ground plane of an adjacent transition layer;

an electrically conductive transmission line including:
a coplanar waveguide portion electrically coupled to a microstrip portion;
a capacitor electrically coupled to the microstrip portion, the capacitor configured to block direct current while allowing alternating current to pass;

the signal vias of the multilayer vertical transition; and
a signal pin electrically coupled to the signal vias, wherein the signal pin is configured to be electrically coupled to a printed circuit board (PCB) via a PCB signal trace deposited on the PCB; and

wherein an adjacent ground plane of the plurality of transition layers is configured to be adjacent to a package-PCB interface formed when the electronics package is mounted to the PCB, the adjacent ground plane including a transition ground cut, and wherein the transition ground cut provides clearance between the adjacent ground plane and the signal pin.

2. The electronics package of claim 1 , wherein the signal cuts are substantially circular.

3. The electronics package of claim 1 , wherein the transition ground cut is formed along an edge of the adjacent ground plane.

4. The electronics package of claim 1 , wherein the transition ground cut is substantially rectangular.

5. The electronics package of claim 1 , wherein the electronics package includes a ceramic material.

6. The electronics package of claim 1 , further including:
a ground plane adjacent to the capacitor, the adjacent ground plane including a capacitor ground cut adjacent to the capacitor.

7. The electronics package of claim 1 , wherein the signal vias of the plurality of transition layers are axially aligned.

8. The electronics package of claim 1 , wherein the signal vias of the plurality of transition layers are staggered.

9. The electronics package of claim 1 , wherein the electronics package is electrically coupled to an optoelectronic circuit.

10. Multiple component circuitry comprising:
a printed circuit board (PCB);
a PCB signal trace disposed on the PCB;
an integrated circuit package mounted on the PCB, the integrated circuit package comprising:
a multilayer vertical transition, the multilayer vertical transition including:
a plurality of transition layers, each transition layer of the plurality of transition layers including:
an insulating layer;
a signal via, wherein:
 the signal via passes through the insulating layer; and
 the signal via is electrically coupled with the signal via of an adjacent transition layer;
a ground plane disposed at a face of the insulating layer, the ground plane including a signal cut, wherein the signal cut provides clearance between the ground plane and the signal via; and
a plurality of ground vias, wherein the ground vias are configured to electrically couple the ground plane of the transition layer with the ground plane of an adjacent transition layer;

an electrically conductive transmission line, the transmission line including:
a coplanar waveguide portion electrically coupled to a microstrip portion;
a capacitor electrically coupled to the microstrip portion, the capacitor configured to block direct current while allowing alternating current to pass;
the signal vias of the multilayer vertical transition; and
a signal pin electrically coupled to the signal vias, wherein the signal pin is configured to be electrically coupled to the PCB signal trace at a package-PCB interface; and

wherein an adjacent ground plane of the plurality of transition layers is adjacent to the package-PCB interface, the adjacent ground plane including a transition ground cut, wherein the transition ground cut provides clearance between the adjacent ground plane and the signal pin at the package-PCB interface.

11. The multiple component circuitry of claim 10 , further comprising an optoelectronic circuit package mounted on the PCB.

12. The multiple component circuitry of claim 10 , wherein the signal cut forms a substantially circular opening in the ground plane.

13. The multiple component circuitry of claim 10 , wherein the signal vias of the plurality of transition layers are axially aligned.

14. The multiple component circuitry of claim 10 , wherein the signal vias of the plurality of transition layers are staggered.

Assignees

• Song Yunpeng
• Liu Yongsheng
• Deng Hongyu
• Finisar Corp

Inventors

• Song Yunpeng
• Liu Yongsheng
• Deng Hongyu

Classifications

• H05K1/0243 Primary

  Printed circuits associated with mounted high frequency components · CPC title

• H01P5/08 Primary

  for linking dissimilar lines or devices (H01P1/16, H01P5/04 take precedence; linking lines of the same kind but with different dimensions H01P5/02) · CPC title

• H01P3/08

  Microstrips; Strip lines · CPC title

• H05K1/0251

  related to vias or transitions between vias and transmission lines · CPC title

• H05K2201/09236

  Parallel layout · CPC title