IC class T0-T2 taps with and without topology selection logic

Patent metadata

Field	Value
Publication number	US-9009554-B2
Application number	US-201414340908-A
Country	US
Kind code	B2
Filing date	Jul 25, 2014
Priority date	Jul 29, 2008
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

First claim

What is claimed is:

1. An integrated circuit comprising:
(A) a first test clock lead, a second test clock lead, a test mode select lead, a test data in lead, and a test data out lead;
(B) a first test access port having a clock input connected to the first test clock lead and being free of the second test clock lead, having a mode input connected to the test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data out…

Assignees

• Texas Instruments Inc

Inventors

• Swoboda Gary L

Classifications

• G06F11/3656

  Physics · mapped topic

• G01R31/3177 Primary

  Physics · mapped topic

• G06F2201/88

  Physics · mapped topic

• G06F11/27

  Physics · mapped topic

• G06F11/22

  Physics · mapped topic