Pulse-latch based bus design for increased bandwidth
US-2015363352-A1 · Dec 17, 2015 · US
US9003071B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9003071-B2 |
| Application number | US-201313900037-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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A method implemented by a non-volatile memory (NVM) controller comprising obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function, determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space, and accessing the namespace based on the mapping between the PCIe function and the namespace.
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I claim: 1. A method implemented by a non-volatile memory (NVM) controller comprising: obtaining a NVM express (NVMe) command comprising a namespace identifier (NSID) from a host memory via a peripheral component interconnect express (PCIe) function; determining a mapping between the PCIe function and a namespace identified by the NSID based on a data structure stored in a PCIe memory address space; and accessing the namespace based on the mapping between the PCIe function and…
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