Memory cell sensing

Patent metadata

Field	Value
Publication number	US-9001577-B2
Application number	US-201213486767-A
Country	US
Kind code	B2
Filing date	Jun 1, 2012
Priority date	Jun 1, 2012
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

First claim

What is claimed is:

1. A method for operating a memory, comprising:
determining a data state of a first memory cell coupled to a first data line;
determining a data state of a third memory cell coupled to a third data line;
transferring the determined data state of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line; and
determining a data state of the second memory cell based, at least partially, on the at least one transferred determined data state stored in the data line control unit.

2. The method of claim 1 , wherein determining the data state of the second memory cell comprises determining the data state of the second memory cell using the data line control unit.

3. The method of claim 1 , including determining the data states of the first memory cell and the third memory cell in response to a request to sense the data state of the second memory cell.

4. The method of claim 1 , wherein determining the data state of the second memory cell comprises applying a plurality of sensing voltages to a selected access line to which the second memory cell is coupled to output a number of data states.

5. The method of claim 4 , including selecting one of the number of data states based, at least partially, on the transferred determined data.

6. The method of claim 1 , further comprising programming the first memory cell, the second memory cell, and the third memory cell in accordance with a shielded data line technique prior to determining the data states of the first, second, and third memory cells.

7. The method of claim 1 , wherein operating the memory includes operating the first, second, and the third memory cells as multilevel memory cells (MLCs).

8. The method of claim 1 , including selectively coupling the data line control unit to the first data line or the second data line.

9. The method of claim 1 , wherein transferring the determined data state of the at least one of the first and the third memory cells to the data line control unit comprises transferring to a dynamic data cache.

10. A method for operating a memory, comprising:
determining a data state stored by a first memory cell coupled to a first data line and a second memory cell coupled to a third data line;
transferring the determined data state stored by at least one of the first memory cell and the second memory cell for storage in a first data line control unit selectively coupled to a second data line to which a target memory cell is coupled, wherein the second data line is adjacent to the first data line and the third data line; and
sensing a data state stored by the target memory cell using a plurality of sensing voltages applied to a selected access line to which the first memory cell, the second memory cell, and the target memory cell are coupled, the sensing voltages based, at least partially, on potential data state combinations of the first and second memory cells.

11. The method of claim 10 , including determining the potential data state combinations of the first and second memory cells based on a combination of charges storable on the first and second memory cells.

12. The method of claim 10 , including determining the potential data state combinations of the first and second memory cells based on a combination of an erased state and non-erased states for each of the first and second memory cells.

13. The method of claim 10 , wherein determining data states stored by the first memory cell coupled to the first data line and the second memory cell coupled to the third data line comprises determining data states stored by the first memory cell and the target memory cell that are selectively coupled to the first data line control unit and the second memory cell that is selectively coupled to a second data line control unit.

14. The method of claim 13 , further comprising selectively coupling the first data line control unit and the second data line control unit to a data transfer device.

15. The method of claim 14 , further comprising transferring, via the data transfer device, the determined data state stored by the second memory cell from the second data line control unit to the first data line control unit selectively coupled to the first memory cell and the target memory cell.

16. The method of claim 15 , further comprising determining a data state of the target memory cell using the first data line control unit.

17. A method for operating a memory, comprising:
determining a data state of a first memory cell coupled to a first data line in response to a request to sense a data state of a target memory cell coupled to a second data line adjacent the first data line, wherein the first and second data lines are selectively coupled to a first shared data line control unit;
determining a data state of a second memory cell coupled to a third data line adjacent to the second data line in response to the request to sense the data state of the target memory cell, wherein the third data line is selectively coupled to a second shared data line control unit;
transferring the determined data state of the second memory cell from the second shared data line control unit to the first shared data line control unit; and
determining the data state of the target memory cell based, at least partially, on the transferred determined data state of the second memory cell stored in the first shared data line control unit.

18. The method of claim 17 , including transferring the determined data state of the second memory cell to the first shared data line control unit via a data transfer device selectively coupled between an interface line of the first shared data line control unit and an interface line of the second shared data line control unit.

19. The method of claim 18 , including transferring the determined data state of the second memory cell to the first shared data line control unit responsive to an enable signal provided to the data transfer device.

20. The method of claim 17 , wherein determining the data state of the target memory cell is based, at least partially, on the first shared data line control unit using the transferred determined data state of the second memory cell and on the determined data state of the first memory cell.

21. The method of claim 17 , wherein determining the data state of the target memory cell comprises applying a plurality of sensing voltages to a selected access line to which the first memory cell, the target memory cell, and the second memory cell are coupled, the plurality of sensing voltages based, at least partially, on potential data state combinations of the first and second memory cells.

22. The method of claim 21 , wherein the plurality of sensing voltages correspond to a number of possible data states to which the first and second memory cells are programmable, and wherein the method includes selecting one of a number of output data states based, at least partially, on the determined data states of the first and second memory cells.

23. An apparatus, comprising:
a first data line coupled to a first memory cell and selectively to a first data line control unit;
a second data line coupled to a second memory cell and selectively to the first data line control unit, the second data line adjacent to the first data line;
a third data line coupled to a third memory cell and s

Assignees

• Goldman Matthew
• Kalavade Pranav
• Chandrasekhar Uday
• Helm Mark A
• Micron Technology Inc

Inventors

• Goldman Matthew
• Kalavade Pranav
• Chandrasekhar Uday
• Helm Mark A

Classifications

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G06F2212/452

  Instruction code · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title