Method for fabricating semiconductor device by damascene process

Patent metadata

Field	Value
Publication number	US-8999845-B2
Application number	US-201414451014-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Dec 9, 2011
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure;
forming a plurality of conductive lines filled in the trenches;
forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns…

Assignees

• Sk Hynix Inc

Inventors

• Yu Jae-Seon

Classifications

• H10W20/087

  Electricity · mapped topic

• H10W20/076

  Electricity · mapped topic

• H10W20/056

  Electricity · mapped topic

• H10W20/069 Primary

  Electricity · mapped topic

• H10B12/482

  Electricity · mapped topic