Sidewall-free CESL for enlarging ILD gap-fill window

Patent metadata

Field	Value
Publication number	US-8999834-B2
Application number	US-201414185547-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Jun 15, 2009
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.

First claim

What is claimed is:

1. A method comprising:
providing a first gate strip over a substrate and having a gate spacer on a sidewall of the first gate strip;
forming a contact etch stop layer (CESL) over the gate strip and on a first sidewall of the gate spacer, a second sidewall of the gate spacer is opposite the first sidewall of the gate spacer and nearest the first gate strip, wherein a top portion of the CESL extends over the gate strip and a bottom portion of the CESL extends…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chung Han-Pin
• Hsieh Bor Chiuan
• Wang Shiang-Bau
• Tao Hun-Jan

Classifications

• H10D84/83125

  Electricity · mapped topic

• H10W20/098 Primary

  Electricity · mapped topic

• H10W20/077

  Electricity · mapped topic

• H10W20/074

  Electricity · mapped topic

• H10W20/40

  Electricity · mapped topic