Defect scan and manufacture test

US8996954B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8996954-B2
Application numberUS-201314054662-A
CountryUS
Kind codeB2
Filing dateOct 15, 2013
Priority dateMar 31, 2010
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for determining whether a portion of a storage device includes a defect, comprising: a processor configured to: read data from the portion of the storage device; correct the read data using a decoder; obtain reference data associated with the portion; compare the reference data and the read data to determine a number of error bits and a number of error symbols associated with the portion; compute an error ratio, wherein the error ratio comp…

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What does patent US8996954B2 cover?
A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds …
Who is the assignee on this patent?
Sk Hynix Memory Solutions Inc
What technology area does this patent fall under?
Primary CPC classification G11C29/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).