Semiconductor test system and method
US-9222977-B2 · Dec 29, 2015 · US
On-chip service processor
US8996938B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996938-B2 |
| Application number | US-201113027009-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2011 |
| Priority date | Mar 25, 1998 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising: one or more logic blocks configured to generate one or more system operation signals at one or more system operation clock rates; a service processor unit configured to perform one or more debug operations on one or more of the logic blocks, the service processor unit comprising: a control unit configured to control the service processor unit; a memory; an analysis engine; and a bus interface; and a multiplicity…
Assignees
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G01R31/318572Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8996938B2 cover?
- An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-defina…
- Who is the assignee on this patent?
- Dervisoglu Bulent, Cooke Laurence H, Arat Vacit, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G01R31/318572. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).