Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
Bypassing memory requests to a main memory
US8996818B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8996818-B2 |
| Application number | US-201213709044-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 9, 2012 |
| Priority date | Dec 9, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Some embodiments include a computing device with a control circuit that handles memory requests. The control circuit checks one or more conditions to determine when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory. When the memory request should be bypassed to a main memory, the control circuit sends the memory request to the main memory. Otherwise, the control circuit sends the memory request to the cache memory.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for handling memory requests, comprising: in a control circuit, performing operations for: when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory, sending the memory request to the main memory; otherwise, sending the memory request to the cache memory; wherein the memory request should be bypassed to the main memory instead of sending the memory request to the cache memory when: the me…
Assignees
Inventors
Classifications
- G06F12/0888Primary
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8996818B2 cover?
- Some embodiments include a computing device with a control circuit that handles memory requests. The control circuit checks one or more conditions to determine when a memory request should be bypassed to a main memory instead of sending the memory request to a cache memory. When the memory request should be bypassed to a main memory, the control circuit sends the memory request to the main memo…
- Who is the assignee on this patent?
- Advanced Micro Devices Inc, Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0888. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).