Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
Digital second-order CDR circuits
US8995597B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8995597-B2 |
| Application number | US-201213679123-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 16, 2012 |
| Priority date | Apr 16, 2010 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases.
First claim
Opening claim text (preview).
What is claimed is: 1. A clock and data recovery circuit comprising: a finite state machine (FSM) comprising: an early/late determination circuit configured to output a first-order phase code; and a second-order accumulator configured to receive and accumulate first-order phase codes of different FSM cycles, and to generate a second-order phase code, wherein the second-order phase code is a non-integer. 2. The clock and data recovery circuit of claim 1…
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- H04L7/0337Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8995597B2 cover?
- A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from t…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H04L7/0337. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).