Semiconductor device with refresh control circuit

Patent metadata

Field	Value
Publication number	US-8995216-B2
Application number	US-201213531807-A
Country	US
Kind code	B2
Filing date	Jun 25, 2012
Priority date	Dec 18, 2008
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory cell array comprising a plurality of word lines, a plurality of bit lines each intersecting the word lines, and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines;
a row-based control circuit taking an active state, to access the memory cell array, and a standby state, to suspend accessing the memory cell array, the row-based control circuit being equipped wi…

Assignees

• Furutani Kiyohiro
• Ps4 Luxco Sarl

Inventors

• Furutani Kiyohiro

Classifications

• G11C11/406 Primary

  Physics · mapped topic

• G11C8/06 Primary

  Physics · mapped topic

• G11C11/40615

  Physics · mapped topic

• G11C8/08

  Physics · mapped topic

• G11C8/18

  Physics · mapped topic