Writing method and erasing method of fusion memory
US-12002500-B2 · Jun 4, 2024 · US
Semiconductor device and control method of the same
US8995215B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8995215-B2 |
| Application number | US-201314081987-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 15, 2013 |
| Priority date | Jun 28, 2005 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a semiconductor device, comprising: fabricating a first current-voltage conversion circuit coupled to a core cell data line; forming a second current-voltage conversion circuit coupled a reference cell data line; and manufacturing a charging circuit coupled to the reference cell data line, wherein said charging circuit is operable to pre-charge the reference cell data line, and said reference cell data line is pre-charged faster…
Assignees
Inventors
Classifications
Electricity · mapped topic
- G11C16/0466Primary
Physics · mapped topic
- H01L27/1052Primary
Electricity · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8995215B2 cover?
- The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first cur…
- Who is the assignee on this patent?
- Spansion Llc
- What technology area does this patent fall under?
- Primary CPC classification G11C16/0466. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).